Semiconductor Device and Method for Manufacturing the Same

ABSTRACT

A semiconductor device includes a pixel electrode and a transistor which includes a first gate electrode, a first insulating layer over the first gate electrode, a semiconductor layer over the first insulating layer, a second insulating layer over the semiconductor layer, and a second gate electrode. The pixel electrode and the second gate electrode are provided over the second insulating layer. The first gate electrode has a region overlapping with the semiconductor layer with the first insulating layer provided therebetween. The second gate electrode has a region overlapping with the semiconductor layer with the second insulating layer provided therebetween. A first region is at least part of a region where the second gate electrode overlaps with the semiconductor layer. A second region is at least part of a region where the pixel electrode is provided. The second insulating layer is thinner in the first region than in the second region.

This application is a continuation of U.S. application Ser. No.15/467,231, filed on Mar. 23, 2017 which is a continuation of copendingU.S. application Ser. No. 15/360,226, filed on Nov. 23, 2016 which is acontinuation of U.S. application Ser. No. 14/718,333, filed on May 21,2015 (now U.S. Pat. No. 9,508,862 issued Nov. 29, 2016) which is acontinuation of U.S. application Ser. No. 14/221,753, filed on Mar. 21,2014 (now U.S. Pat. No. 9,040,995 issued May 26, 2015) which is acontinuation of U.S. application Ser. No. 13/462,945, filed on May 3,2012 (now U.S. Pat. No. 8,680,529 issued Mar. 25, 2014) which areincorporated herein by reference.

BACKGROUND OF THE INVENTION 1. Field of the Invention

The present invention relates to semiconductor devices, display devices,light-emitting devices, and methods for manufacturing these devices. Inparticular, the present invention relates to semiconductor devices,display devices, and light-emitting devices each including a transistor,and methods for manufacturing these devices. The present inventionrelates to electronic devices including the semiconductor devices, thedisplay devices, or the light-emitting devices.

2. Description of the Related Art

It is known that the on-state current of a transistor including gateelectrodes above and below with a semiconductor layer providedtherebetween can be increased and that the off-state current of thetransistor can be decreased by control of the threshold voltage. Atransistor with such a structure is referred to as a double-gatetransistor or a dual-gate transistor. In the following description, atransistor with such a structure is also referred to as a bottom-gatetransistor with a back gate electrode.

A bottom-gate transistor with a back gate electrode can be used in, forexample, a display device (see FIG. 7 in Patent Document 1).

REFERENCE

-   -   Patent Document 1: Japanese Published Patent Application No.        2010-109342.

SUMMARY OF THE INVENTION

In a display device disclosed in Patent Document 1, in order to increasethe aperture ratio or to reduce noise to a pixel electrode, aplanarization insulating layer is formed over a transistor and the pixelelectrode is formed over the planarization insulating layer. Here, aback gate electrode of the transistor is formed in a position which isbelow the planarization insulating layer and is close to a semiconductorlayer (a semiconductor layer in which a channel is formed) of thetransistor.

In the display device disclosed in Patent Document 1, the back gateelectrode is formed using a layer different from the layer of the pixelelectrode. Thus, the display device disclosed in Patent Document 1 has aproblem in that the number of manufacturing steps is increased ascompared to a display device including a transistor which does not havea back gate electrode.

When the back gate electrode and the pixel electrode are formed usingthe same layer in order to inhibit an increase in the number ofmanufacturing steps, the planarization insulating layer exists betweenthe back gate electrode and the semiconductor layer of the transistor.Since the planarization insulating layer is generally thick, there is aproblem in that the back gate electrode cannot function well.

It is an object of one embodiment of the present invention tomanufacture a semiconductor device including a bottom-gate transistorwith a back gate electrode in fewer steps. Alternatively, it is anobject of one embodiment of the present invention to provide asemiconductor device including a bottom-gate transistor with a back gateelectrode that can be manufactured in fewer steps. Alternatively, it isan object of one embodiment of the present invention to provide asemiconductor device where a strong electric field can be applied to asemiconductor layer by a back gate electrode. Alternatively, it is anobject of one embodiment of the present invention to provide asemiconductor device where the threshold voltage is controlled.Alternatively, it is an object of one embodiment of the presentinvention to provide a semiconductor device which is easily normallyoff. Alternatively, it is an object of one embodiment of the presentinvention to provide a semiconductor device including a transistor whoseon-state current is high. Alternatively, it is an object of oneembodiment of the present invention to provide a semiconductor deviceincluding a transistor capable of inhibiting the incidence of light on achannel or the like. Alternatively, it is an object of one embodiment ofthe present invention to provide a semiconductor device including atransistor which is not easily degraded. Alternatively, it is an objectof one embodiment of the present invention to provide a semiconductordevice where the thickness of an insulating layer provided over achannel of a transistor is varied using a half-tone mask or a gray-tonemask. Alternatively, it is an object of one embodiment of the presentinvention to provide a better semiconductor device while inhibiting anincrease in the number of steps. Alternatively, it is an object of oneembodiment of the present invention to provide a semiconductor devicewhere an increase in cost is inhibited by inhibiting an increase in thenumber of steps. Alternatively, it is an object of one embodiment of thepresent invention to provide a display device capable of displaying animage accurately by using a transistor whose off-state current is low.Alternatively, it is an object of one embodiment of the presentinvention to provide a display device having a high aperture ratio.Alternatively, it is an object of one embodiment of the presentinvention to provide a semiconductor device in which noise to a pixelelectrode is low. Alternatively, it is an object of one embodiment ofthe present invention to provide a semiconductor device in which aninsulating layer is thicker in a portion below a pixel electrode than ina portion below a back gate electrode.

Note that the description of these objects does not impede the existenceof other objects. Note that in one embodiment of the present invention,there is no need to achieve all the objects. Other objects will beapparent from and can be derived from the description of thespecification, the drawings, the claims, and the like.

One embodiment of the present invention is a semiconductor device thatincludes a transistor and a pixel electrode. The transistor includes afirst gate electrode, a first insulating layer over the first gateelectrode, a semiconductor layer over the first insulating layer, asecond insulating layer over the semiconductor layer, and a second gateelectrode over the second insulating layer. The first gate electrode hasa region overlapping with the semiconductor layer with the firstinsulating layer provided therebetween. The second gate electrode has aregion overlapping with the semiconductor layer with the secondinsulating layer provided therebetween. The pixel electrode is providedover the second insulating layer. A first region is at least part of aregion where the second gate electrode at least partly overlaps with atleast part of the semiconductor layer. A second region is at least partof a region where the pixel electrode is provided. The second insulatinglayer is thinner in the first region than in the second region.

The transistor can further include a first electrode and a secondelectrode. One of the first electrode and the second electrode can be asource electrode, and the other of the first electrode and the secondelectrode can be a drain electrode. The pixel electrode may beelectrically connected to the transistor through an opening in thesecond insulating layer.

The second insulating layer may include either one or both a colorfilter and a black matrix.

One embodiment of the present invention is a method for manufacturing asemiconductor device. The method includes a step of forming a first gateelectrode over an insulating surface, a step of forming a firstinsulating layer over the first gate electrode, a step of forming asemiconductor layer over the first insulating layer so that thesemiconductor layer at least partly overlaps with at least part of thefirst gate electrode with the first insulating layer providedtherebetween, a step of forming a second insulating layer including afirst region and a second region, over the semiconductor layer, and astep of forming a second gate electrode and a pixel electrode over thesecond insulating layer so that the second gate electrode at leastpartly overlaps with at least part of the semiconductor layer with thefirst region of the second insulating layer provided therebetween and atleast part of the pixel electrode is provided over at least part of thesecond region of the second insulating layer. The first region of thesecond insulating layer is thinner than the second region of the secondinsulating layer.

One embodiment of the present invention is a method for manufacturing asemiconductor device. The method includes a step of forming a first gateelectrode over an insulating surface, a step of forming a firstinsulating layer over the first gate electrode, a step of forming asemiconductor layer over the first insulating layer so that thesemiconductor layer at least partly overlaps with at least part of thefirst gate electrode with the first insulating layer providedtherebetween, a step of forming a second insulating layer including afirst region, a second region, and a through hole, over thesemiconductor layer, and a step of forming a second gate electrode and apixel electrode over the second insulating layer so that the second gateelectrode at least partly overlaps with at least part of thesemiconductor layer with the first region of the second insulating layerprovided therebetween and the pixel electrode at least partly overlapswith at least part of the second region of the second insulating layerand is in contact with a lower wiring or a lower electrode through thethrough hole. The first region of the second insulating layer is thinnerthan the second region of the second insulating layer.

The second insulating layer may be formed using a half-tone mask, agray-tone mask, a phase shift mask, or a multi-tone mask.

According to one embodiment of the present invention, it is possible tomanufacture a semiconductor device including a bottom-gate transistorwith a back gate electrode in fewer steps. Alternatively, it is possibleto provide a semiconductor device including a bottom-gate transistorwith a back gate electrode that can be manufactured in fewer steps.Alternatively, it is possible to provide a semiconductor device where astrong electric field can be applied to a semiconductor layer by a backgate electrode. Alternatively, it is possible to provide a semiconductordevice where the threshold voltage is controlled. Alternatively, it ispossible to provide a semiconductor device which is easily normally off.Alternatively, it is possible to provide a semiconductor deviceincluding a transistor whose on-state current is high. Alternatively, itis possible to provide a semiconductor device where the thickness of aninsulating layer provided over a channel of a transistor is varied usinga half-tone mask, a gray-tone mask, a phase shift mask, or a multi-tonemask. Alternatively, it is possible to provide a better semiconductordevice while inhibiting an increase in the number of steps.Alternatively, it is possible to provide a semiconductor device where anincrease in cost is inhibited by inhibiting an increase in the number ofsteps. Alternatively, it is possible to provide a display device capableof displaying an image accurately by using a transistor whose off-statecurrent is low. Alternatively, it is possible to provide a displaydevice having a high aperture ratio. Alternatively, it is possible toprovide a display device in which noise to a pixel electrode is low.Alternatively, it is possible to provide a display device in which aninsulating layer is made thicker in a portion below a pixel electrodethan in a portion below a back gate electrode.

BRIEF DESCRIPTION OF THE DRAWINGS

In the accompanying drawings:

FIGS. 1A to 1E are cross-sectional views each illustrating the structureof a semiconductor device;

FIGS. 2A to 2E are cross-sectional views each illustrating the structureof a semiconductor device;

FIGS. 3A to 3E are cross-sectional views each illustrating the structureof a semiconductor device;

FIGS. 4A and 4B are cross-sectional views each illustrating thestructure of a semiconductor device;

FIGS. 5A and 5B are cross-sectional views each illustrating thestructure of a semiconductor device;

FIGS. 6A to 6E are cross-sectional views each illustrating the structureof a semiconductor device;

FIGS. 7A to 7E are cross-sectional views each illustrating the structureof a semiconductor device;

FIGS. 8A to 8E are cross-sectional views each illustrating the structureof a semiconductor device;

FIGS. 9A to 9E are cross-sectional views each illustrating the structureof a semiconductor device;

FIGS. 10A to 10E are cross-sectional views each illustrating thestructure of a semiconductor device;

FIGS. 11A to 11E are cross-sectional views each illustrating thestructure of a semiconductor device;

FIGS. 12A to 12E are cross-sectional views each illustrating thestructure of a semiconductor device;

FIGS. 13A to 13E are cross-sectional views each illustrating thestructure of a semiconductor device;

FIGS. 14A to 14E are cross-sectional views each illustrating thestructure of a semiconductor device;

FIGS. 15A to 15E are cross-sectional views each illustrating thestructure of a semiconductor device;

FIGS. 16A to 16E are cross-sectional views each illustrating thestructure of a semiconductor device;

FIGS. 17A to 17E are cross-sectional views each illustrating thestructure of a semiconductor device;

FIGS. 18A to 18E are cross-sectional views each illustrating thestructure of a semiconductor device;

FIGS. 19A to 19D are cross-sectional views each illustrating thestructure of a semiconductor device;

FIGS. 20A to 20D are cross-sectional views each illustrating thestructure of a semiconductor device;

FIGS. 21A to 21D are cross-sectional views each illustrating thestructure of a semiconductor device;

FIGS. 22A to 22E are cross-sectional views each illustrating thestructure of a semiconductor device;

FIGS. 23A to 23E are cross-sectional views each illustrating thestructure of a semiconductor device;

FIGS. 24A to 24E are cross-sectional views each illustrating thestructure of a semiconductor device;

FIGS. 25A to 25E are cross-sectional views each illustrating thestructure of a semiconductor device;

FIGS. 26A to 26E are cross-sectional views each illustrating thestructure of a semiconductor device;

FIGS. 27A to 27E are cross-sectional views each illustrating thestructure of a semiconductor device;

FIGS. 28A to 28E are cross-sectional views each illustrating thestructure of a semiconductor device;

FIGS. 29A and 29B are cross-sectional views each illustrating thestructure of a semiconductor device;

FIGS. 30A and 30B are cross-sectional views each illustrating thestructure of a semiconductor device;

FIGS. 31A to 31E are cross-sectional views each illustrating thestructure of a semiconductor device;

FIGS. 32A to 32E are cross-sectional views each illustrating thestructure of a semiconductor device;

FIGS. 33A to 33E are cross-sectional views each illustrating thestructure of a semiconductor device;

FIGS. 34A to 34E are cross-sectional views each illustrating thestructure of a semiconductor device;

FIGS. 35A to 35E are cross-sectional views each illustrating thestructure of a semiconductor device;

FIGS. 36A to 36E are cross-sectional views each illustrating thestructure of a semiconductor device;

FIGS. 37A to 37E are cross-sectional views each illustrating thestructure of a semiconductor device;

FIGS. 38A to 38E are cross-sectional views each illustrating thestructure of a semiconductor device;

FIGS. 39A to 39E are cross-sectional views each illustrating thestructure of a semiconductor device;

FIGS. 40A to 40E are cross-sectional views each illustrating thestructure of a semiconductor device;

FIGS. 41A to 41E are cross-sectional views each illustrating thestructure of a semiconductor device;

FIGS. 42A to 42E are cross-sectional views each illustrating thestructure of a semiconductor device;

FIGS. 43A to 43E are cross-sectional views each illustrating thestructure of a semiconductor device;

FIGS. 44A to 44D are cross-sectional views each illustrating thestructure of a semiconductor device;

FIGS. 45A to 45D are cross-sectional views each illustrating thestructure of a semiconductor device;

FIGS. 46A to 46D are cross-sectional views each illustrating thestructure of a semiconductor device;

FIGS. 47A to 47D are cross-sectional views each illustrating thestructure of a semiconductor device;

FIGS. 48A to 48E are cross-sectional views each illustrating thestructure of a semiconductor device;

FIGS. 49A to 49E are cross-sectional views each illustrating thestructure of a semiconductor device;

FIGS. 50A to 50E are cross-sectional views each illustrating thestructure of a semiconductor device;

FIGS. 51A to 51E are cross-sectional views each illustrating thestructure of a semiconductor device;

FIGS. 52A and 52B are cross-sectional views each illustrating thestructure of a semiconductor device;

FIG. 53 is a top view illustrating the structure of a semiconductordevice;

FIG. 54 is a top view illustrating the structure of a semiconductordevice;

FIGS. 55A to 55H are circuit diagrams each illustrating the structure ofa semiconductor device;

FIGS. 56A to 56C are circuit diagrams each illustrating the structure ofa semiconductor device;

FIGS. 57A and 57B are circuit diagrams each illustrating the structureof a semiconductor device;

FIGS. 58A to 58D are cross-sectional views each illustrating thestructure of a semiconductor device;

FIGS. 59A to 59E illustrate a method for manufacturing a semiconductordevice;

FIGS. 60A to 60E illustrate a method for manufacturing a semiconductordevice;

FIGS. 61A to 61D illustrate a method for manufacturing a semiconductordevice;

FIGS. 62A to 62E illustrate a method for manufacturing a semiconductordevice;

FIGS. 63A to 63E illustrate a method for manufacturing a semiconductordevice;

FIGS. 64A to 64E illustrate a method for manufacturing a semiconductordevice;

FIGS. 65A to 65D are cross-sectional views each illustrating thestructure of a semiconductor device;

FIGS. 66A to 66C are cross-sectional views each illustrating thestructure of a semiconductor device;

FIGS. 67A to 67H illustrate electronic devices;

FIGS. 68A to 68H illustrate electronic devices;

FIGS. 69A to 69E each illustrate the structure of an oxide semiconductorlayer;

FIGS. 70A to 70C illustrate the structure of an oxide semiconductorlayer;

FIGS. 71A to 71C illustrate the structure of an oxide semiconductorlayer; and

FIG. 72 illustrates a display module.

DETAILED DESCRIPTION OF THE INVENTION

Embodiments of the present invention will be described in detail belowwith reference to the drawings. Note that the present invention is notlimited to the following description. It will be readily appreciated bythose skilled in the art that modes and details of the present inventioncan be modified in various ways without departing from the spirit andscope of the present invention. The present invention therefore shouldnot be construed as being limited to the following description of theembodiments. Note that in structures described below, the same portionsor portions having similar functions are denoted by the same referencenumerals in different drawings, and the description thereof is omitted.

Note that content (or may be part of the content) described in oneembodiment may be applied to, combined with, or replaced by differentcontent (or may be part of the different content) described in theembodiment and/or content (or may be part of the content) described inone or more different embodiments.

Note that the structure of a diagram (or may be part of the diagram)illustrated in one embodiment can be combined with the structure ofanother part of the diagram, the structure of a different diagram (ormay be part of the different diagram) illustrated in the embodiment,and/or the structure of a diagram (or may be part of the diagram)illustrated in one or more different embodiments.

Note that size, thickness, or regions in the drawings are exaggeratedfor clarity in some cases. Thus, one aspect of an embodiment of thepresent invention is not limited to such scales. Alternatively, thedrawings are perspective views of ideal examples. Thus, one aspect of anembodiment of the present invention is not limited to shapes and thelike illustrated in the drawings. For example, a variation in shape dueto a manufacturing technique or dimensional deviation can be included.

Note that an explicit expression “X and Y are connected” means that Xand Y are electrically connected, X and Y are functionally connected,and where X and Y are directly connected. Here, each of X and Y is anobject (e.g., a device, an element, a circuit, a wiring, an electrode, aterminal, a conductive film, or a layer). Accordingly, a connectionrelation other than those illustrated in drawings and texts is alsoincluded, without limitation to a predetermined connection relation, forexample, the connection relation illustrated in the drawings and thetexts.

For example, in the case where X and Y are electrically connected, oneor more elements which enable an electrical connection between X and Y(e.g., a switch, a transistor, a capacitor, an inductor, a resistor,and/or a diode) can be connected between X and Y.

For example, in the case where X and Y are functionally connected, oneor more circuits which enable a functional connection between X and Ycan be connected between X and Y. Note that for example, in the casewhere a signal output from X is transmitted to Y even when anothercircuit is provided between X and Y, X and Y are functionally connected.

Note that an explicit expression “X and Y are electrically connected”means that X and Y are electrically connected, X and Y are functionallyconnected, and X and Y are directly connected. That is, the explicitexpression “X and Y are electrically connected” is the same as anexplicit simple expression “X and Y are connected”.

Note that even when independent components are electrically connected toeach other in a circuit diagram, there is the case where one conductivelayer has functions of a plurality of components (e.g., a wiring and anelectrode), such as the case where part of a wiring functions as anelectrode. The expression “electrically connected” in this specificationalso means that one conductive layer has functions of a plurality ofcomponents.

Embodiment 1

In this embodiment, one aspect of a semiconductor device or the like(e.g., a display device or a light-emitting device) in the presentinvention is described with reference to drawings.

FIG. 1A is a cross-sectional view of a semiconductor device in oneembodiment of the present invention. The semiconductor device includes atransistor 100 and an electrode 110 over an insulating surface (or aninsulating substrate) 200. The transistor 100 includes an electrode 101,an insulating layer 102 over the electrode 101, a semiconductor layer103 over the insulating layer 102, an insulating layer 105 over thesemiconductor layer 103, and an electrode 106 over the insulating layer105. The electrode 101 has a region overlapping with the semiconductorlayer 103 with the insulating layer 102 provided therebetween. Theelectrode 106 has a region overlapping with the semiconductor layer 103with the insulating layer 105 provided therebetween. The electrode 110is provided over the insulating layer 105. A region 121 is at least partof a region where the electrode 106 at least partly overlaps with atleast part of the semiconductor layer 103. A region 122 is at least partof a region where the electrode 110 is provided. The insulating layer105 is thinner in the region 121 than in the region 122. It can also besaid that the insulating layer 105 includes the region 121 and theregion 122 thicker than the thin region 121, the region 121 is at leastpart of a region where the electrode 106 overlaps with part of thesemiconductor layer 103, and that the region 122 at least partlyoverlaps with the electrode 110.

Here, the electrode 101 and the electrode 106 can function as a firstgate electrode and a second gate electrode (a back gate electrode) ofthe transistor 100, respectively. The electrode 110 can function as apixel electrode. The electrode 106 overlaps with the semiconductor layer103 with the thin region of the insulating layer 105 (the region 121)provided therebetween; thus, the electrode 106 can function well as aback gate electrode. The electrodes 110 and 106 may be formed by etchingof one conductive film. In that case, the electrodes 110 and 106 havethe same material and substantially the same thickness. Alternatively,the electrodes 110 and 106 may be formed by etching of differentconductive films. In the case where one conductive film is etched, thenumber of processes can be reduced.

Note that the transistor preferably includes both the first gateelectrode and the second gate electrode (the back gate electrode).However, one aspect of an embodiment of the present invention is notlimited thereto. It is possible for the transistor to have one of thefirst gate electrode and the second gate electrode (the back gateelectrode) but not to have the other electrode. For example, asillustrated in FIG. 66C, a structure where the transistor does notinclude the electrode 106 may be employed. Even in such a case, thetransistor can operate correctly.

In FIG. 1A, the transistor 100 further includes electrodes 104 a and 104b. One of the electrodes 104 a and 104 b can be a source electrode, andthe other electrode can be a drain electrode. In FIG. 1A, the electrodes104 a and 104 b are provided over the semiconductor layer 103 (forexample, the electrodes 104 a and 104 b are provided to be in contactwith an upper surface and a side surface of the semiconductor layer103). A lower surface of the semiconductor layer 103 is not in contactwith the electrodes 104 a and 104 b.

Note that the transistor preferably includes both the source electrodeand the drain electrode. However, one aspect of an embodiment of thepresent invention is not limited thereto. It is possible for thetransistor to have one of the source electrode and the drain electrodebut not to have the other electrode, or to have neither of theelectrodes. Even in such a case, the transistor whose channel is formedin the semiconductor layer 103 can operate correctly when the transistoris connected to a different element (e.g., a different transistor)through the semiconductor layer 103.

Note that a transistor is an element having at least three terminals: agate, a drain, and a source. The transistor has a channel region betweenthe drain (a drain terminal, a drain region, or a drain electrode) andthe source (a source terminal, a source region, or a source electrode)and current can flow through the drain, the channel region, and thesource. Here, since the source and the drain of the transistor changedepending on the structure, the operating condition, and the like of thetransistor, it is difficult to define which is a source or a drain.Thus, a region which serves as a source or a region which serves as adrain is not referred to as a source or a drain in some cases. In thatcase, one of the source and the drain might be referred to as a firstterminal, a first electrode, or a first region, and the other of thesource and the drain might be referred to as a second terminal, a secondelectrode, or a second region, for example.

The electrode 110 can be electrically connected to the transistor 100through an opening provided in the insulating layer 105.

Note that an explicit expression “Y on X” or “Y over X” does notnecessarily mean that Y is on and in direct contact with X. Theexpression also means that X and Y are not in direct contact with eachother, i.e., another object is provided between X and Y. Here, each of Xand Y is an object (e.g., a device, an element, a circuit, a wiring, anelectrode, a terminal, a conductive film, or a layer).

Thus, for example, an explicit expression “a layer Y on (or over) alayer X” means that the layer Y is on and in direct contact with thelayer X, and another layer (e.g., a layer Z) is on and in direct contactwith the layer X and the layer Y is on and in direct contact with theother layer. Note that another layer (e.g., a layer Z) may be a singlelayer or a plurality of layers (a stack of layers).

Similarly, an explicit expression “Y above X” does not necessarily meanthat Y is on and in direct contact with X, and another object may beprovided therebetween. Thus, for example, an expression “a layer Y abovea layer X” means that the layer Y is on and in direct contact with thelayer X, and another layer (e.g., a layer Z) is on and in direct contactwith the layer X and the layer Y is on and in direct contact with theother layer. Note that another layer (e.g., a layer Z) may be a singlelayer or a plurality of layers (a stack of layers).

Note that the same can be said for an expression “Y under X” or “Y belowX”.

Note that as illustrated in FIG. 9A, a region of the semiconductor layer103 that does not overlap with the electrodes 104 a and 104 b may bemade thin. For example, when etching is performed so that the electrodes104 a and 104 b are formed, part of a surface of the semiconductor layer103 positioned below a layer to be the electrodes 104 a and 104 b may beetched. The transistor in which at least part of a region of thesemiconductor layer 103 that serves as a channel is made thin in thismanner (or the transistor in which a channel protective film is notprovided between an upper portion of the channel and the electrodes 104a and 104 b) might also be referred to as a channel etched transistor.

One aspect of the semiconductor device in the present invention is notlimited to the structure in FIG. 1A. Different structure examples of thesemiconductor device in the present invention are described below. Notethat the same portions as those in FIG. 1A are denoted by the samereference numerals, and the description thereof is omitted.

For example, as illustrated in FIG. 1B, an insulating layer 107 can beprovided between the semiconductor layer 103 and the electrodes 104 aand 104 b. The insulating layer 107 functions as a protective film (achannel protective film) for preventing the semiconductor layer 103(especially, the region of the semiconductor layer 103 that serves as achannel) from being etched when etching is performed so that theelectrodes 104 a and 104 b are formed. The transistor having a channelprotective film might be referred to as a channel protective transistor.In that case, the semiconductor layer 103 can be made thin; thus, thesubthreshold swing (the S value) of the transistor 100 can be improved(decreased).

Note that in the case where the transistor is a channel protectivetransistor, as illustrated in FIG. 65D, the insulating layer 105 can beremoved from the region 121. In that case, the electrode 106 and theinsulating layer 107 are partly in direct contact with each other.Consequently, the electrode 106 functioning as a back gate electrode canapply a stronger electric field to the semiconductor layer 103.

Alternatively, for example, as illustrated in FIG. 2A, the electrodes104 a and 104 b may be formed below the semiconductor layer 103 (forexample, some of upper surfaces and end surfaces of the electrodes 104 aand 104 b may be formed to be in contact with the lower surface of thesemiconductor layer 103). Consequently, the semiconductor layer 103 canbe prevented from being damaged during etching for the electrodes 104 aand 104 b. Alternatively, the semiconductor layer 103 can be made thin,so that the subthreshold swing (the S value) can be improved(decreased).

Alternatively, for example, as illustrated in FIG. 3A, ends 131 a and131 b of the semiconductor layer 103 can be substantially aligned withends 132 a and 132 b of the electrodes 104 a and 104 b. Thesemiconductor layer 103 and the electrodes 104 a and 104 b can be formedby etching of a stack of a semiconductor film and a conductive film overthe semiconductor film with the use of one mask. A photomask havingthree or more regions with different transmittances of light used forexposure (hereinafter such a photomask is referred to as a half-tonemask, a gray-tone mask, a phase shift mask, or a multi-tone mask) can beused as the mask. With the use of the half-tone mask, a region in whichthe semiconductor layer 103 is exposed and a region from which thesemiconductor layer 103 is removed can be formed by etching using onemask. Thus, the number of processes of forming the transistor 100 can befurther reduced, and the cost of the semiconductor device can be furtherreduced. Note that in the case where the semiconductor layer 103 and theelectrodes 104 a and 104 b are formed using the half-tone mask, thesemiconductor layer 103 always exists below the electrodes 104 a and 104b. The end 132 a and/or the end 132 b might be step-like ends.

Alternatively, as illustrated in FIG. 3B, the insulating layer 107functioning as a channel protective film can be provided in thestructure illustrated in FIG. 3A. In this manner, channel protectivefilms can be additionally provided in a variety of transistors which donot have channel protective films in drawings other than FIG. 3B.

Alternatively, for example, as illustrated in FIG. 9A, conductive layers108 a and 108 b can be provided between the semiconductor layer 103 andthe electrodes 104 a and 104 b. The conductive layers 108 a and 108 bcan be formed using, for example, a semiconductor layer to which animpurity element imparting conductivity is added. Alternatively, forexample, the conductive layers 108 a and 108 b can be formed using aconductive metal oxide. Alternatively, for example, the conductivelayers 108 a and 108 b can be formed using a conductive metal oxide towhich an impurity element imparting conductivity is added. Note that inFIG. 1A or the like, an impurity element imparting conductivity may beadded to part of the semiconductor layer 103. Examples of an impurityelement imparting conductivity include phosphorus, arsenic, boron,hydrogen, and tin.

Here, in FIG. 9A, a region of the semiconductor layer 103 that does notoverlap with the electrodes 104 a and 104 b and the conductive layers108 a and 108 b is made thin. This is because part of a surface of thesemiconductor layer 103 positioned below a layer to be the electrodes104 a and 104 b and a layer to be the conductive layers 108 a and 108 bis etched (the transistor in FIG. 9A is a channel etched transistor)when etching is performed so that the electrodes 104 a and 104 b and theconductive layers 108 a and 108 b are formed. Note that a channelprotective film may be provided between the semiconductor layer 103 andthe conductive layers 108 a and 108 b (the transistor in FIG. 9A may bea channel protective transistor) so that the semiconductor layer 103 canbe prevented from being etched.

Note that although the electrodes 110 and 106 are formed using the samelayer in the above structures, this embodiment is not limited thereto.The electrodes 110 and 106 may be formed using different layers.

Alternatively, an insulating layer can be provided between theelectrodes 104 a and 104 b and the semiconductor layer 103 or betweenthe electrodes 104 a and 104 b and the conductive layers 108 a and 108b. Further, an opening may be provided in the insulating layer so thatthe electrodes 104 a and 104 b can be connected to the semiconductorlayer 103 or the electrodes 104 a and 104 b can be connected to theconductive layers 108 a and 108 b.

Note that a variety of substrates can be used as a substrate having aninsulating surface 200, without limitation to a certain type. Examplesof the substrate include a semiconductor substrate (e.g., a singlecrystal substrate or a silicon substrate), an SOI substrate, a glasssubstrate, a quartz substrate, a plastic substrate, a metal substrate, astainless steel substrate, a substrate including stainless steel foil, atungsten substrate, a substrate including tungsten foil, a flexiblesubstrate, an attachment film, paper including a fibrous material, and abase material film.

Note that the transistor 100 may be formed over a substrate, and then,transferred to a different substrate so that the transistor 100 can bedisposed over the different substrate.

As described above, the threshold voltage can be effectively controlledby the back gate electrode of the transistor 100 in FIG. 1A, FIG. 1B,FIG. 2A, FIG. 3A, FIG. 3B, FIG. 9A, or the like. Thus, the transistor100 can be easily normally off. Alternatively, on-state current can beeffectively increased by the back gate electrode. Alternatively,off-state current can be effectively decreased by the back gateelectrode. Alternatively, an on/off ratio can be increased by the backgate electrode. Thus, when a display device has the above structure, thedisplay device can display an image accurately. Alternatively, when adisplay device or a light-emitting device has the above structure andthe insulating layer 105 functions as a planarization film, the apertureratio can be increased.

This embodiment is one of basic structure examples according to oneembodiment of the present invention. Thus, this embodiment can be freelycombined with another embodiment obtained by performing change,addition, modification, removal, application, superordinateconceptualization, or subordinate conceptualization on part or all ofthis embodiment.

Embodiment 2

In this embodiment, one aspect of a semiconductor device or the like(e.g., a display device or a light-emitting device) in the presentinvention is described with reference to drawings.

In the structure described in Embodiment 1 with reference to FIG. 1A,FIG. 1B, FIG. 2A, FIG. 3A, FIG. 3B, FIG. 9A, or the like, the insulatinglayer 105 in the region 122 or part of the region 122 can include astack of a plurality of layers. The insulating layer 105 in the region122 or part of the region 122 includes a stack of m (m is a naturalnumber of 2 or more) layers. The insulating layer 105 in the region 121or part of the region 121 may include a stack of m or less layers or asingle layer. The insulating layer 105 may include an organic insulatinglayer or a stack of an organic insulating layer and an inorganicinsulating layer.

For example, in the structure illustrated in FIG. 1A, FIG. 1B, FIG. 2A,FIG. 3A, FIG. 3B, FIG. 9A, or the like, the insulating layer 105 in theregion 122 may include a stack of layers 105 a and 105 b, and theinsulating layer 105 in the region 121 may include a single layer of thelayer 105 a. The layer 105 b is formed over the layer 105 a. FIG. 1C,FIG. 1D, FIG. 2B, FIG. 3C, FIG. 3D, and FIG. 9B each illustrate such astructure. With such a structure, when only a necessary portion isetched utilizing a difference in sensitivity to etching (etchingselectivity), a stack of the layers 105 a and 105 b can be obtained.Accordingly, the thickness of the insulating layer 105 in each regioncan be easily controlled. Alternatively, the regions can adequately havedifferent functions (e.g., a planarization function, an impurityblocking function, and a light blocking function) depending on filmquality. Alternatively, the number of processes can be reduced when partof the layer is formed using a photosensitive material.

Here, the layer 105 a may be an inorganic insulating layer, and thelayer 105 b may be an organic insulating layer. In that case, since anorganic material is used, the layer 105 b can be thicker than the layer105 a. When the layer 105 a is an inorganic insulating layer (preferablya silicon nitride film), for example, an impurity in the layer 105 b canbe prevented from entering the transistor 100. Alternatively, when thelayer 105 b is an organic insulating layer, the organic insulating layercan function as a planarization layer; thus, unevenness due to thetransistor 100 or the like can be reduced. In this manner, a surface onwhich the electrode 110 is formed can be planarized. Thus, for example,in the case where the electrode 110 is used as a pixel electrode, adisplay defect can be reduced. Alternatively, since the thickness of thelayer 105 b can be increased, noise to the pixel electrode can bereduced. Alternatively, since etching selectivity changes depending onfilm quality, only a necessary portion is selectively etched, so that astack of the layers 105 a and 105 b with a predetermined shape can beobtained.

Alternatively, the layer 105 a and/or the layer 105 b (or part thereof,preferably the layer 105 b) may be a color filter and/or a black matrix.When the layer 105 a and/or the layer 105 b is a color filter and/or ablack matrix, an attachment margin for the substrate provided with thetransistor 100 (the substrate having the insulating surface 200) andanother substrate (e.g., a counter substrate or the like in the displaydevice) can be increased. Alternatively, when a black matrix is providedin the layer 105 a and/or the layer 105 b (or part thereof) near thetransistor 100, light cannot be easily incident on the transistor 100.When light is not easily incident on the transistor 100, the off-statecurrent of the transistor 100 or degradation of the transistor 100 canbe reduced. For example, as illustrated in FIG. 65A, a black matrix 652can be provided in part of the layer 105 b. Note that a plurality ofcolor filters with different colors that overlap with each other can beused as a black matrix.

Note that a color filter and/or a black matrix is preferably formedusing an organic material; thus, the color filter and/or the blackmatrix is preferably formed in the layer 105 b. Note that thisembodiment is not limited thereto, and a light-blocking conductive filmcan be used as the black matrix.

Alternatively, the thickness of the layer 105 a may be smaller than thethickness of the layer 105 b. When the thickness of the layer 105 a ismade smaller, an electric field caused by the electrode 106 can beadequately applied to the channel. Alternatively, when the thickness ofthe layer 105 b is made larger, unevenness due to the transistor 100 orthe like can be adequately reduced.

Alternatively, for example, in the structure illustrated in FIG. 1A,FIG. 1B, FIG. 2A, FIG. 3A, FIG. 3B, FIG. 9A, or the like, the insulatinglayer 105 in the region 122 may include a stack of the layer 105 b and alayer 105 c, and the insulating layer 105 in the region 121 may includea single layer of the layer 105 c. The layer 105 c is formed over thelayer 105 b. FIG. 26A, FIG. 26B, FIG. 27A, FIG. 28A, FIG. 28B, and FIG.34A each illustrate such a structure. With such a structure, when only anecessary portion is etched utilizing a difference in sensitivity toetching (etching selectivity), a stack of the layers 105 b and 105 c canbe obtained. Accordingly, the thickness of the insulating layer 105 ineach region can be easily controlled. Alternatively, the regions canadequately have different functions (e.g., a planarization function, animpurity blocking function, and a light blocking function) depending onfilm quality. Alternatively, the number of processes can be reducedbecause part of the layer can be formed using a photosensitive material.

Here, the layer 105 b may be an organic insulating layer, and the layer105 c may be an inorganic insulating layer. In that case, since anorganic material is used, the layer 105 b can be thicker than the layer105 c. When the layer 105 c is an inorganic insulating layer (preferablya silicon nitride film), an impurity in the layer 105 b can be preventedfrom entering the electrode 106 or a layer over the electrode 106 (e.g.,a liquid crystal layer, an alignment film, or an organic EL layer).Alternatively, when the layer 105 b is an organic insulating layer, theorganic insulating layer can be used as a planarization layer, andunevenness due to the transistor 100 or the like can be reduced. In thismanner, a surface on which the electrode 110 is formed can beplanarized. Thus, for example, in the case where the electrode 110 isused as a pixel electrode, a display defect can be reduced.Alternatively, since the thickness of the layer 105 b can be increased,noise to the pixel electrode can be reduced. Alternatively, sinceetching selectivity changes depending on film quality, only a necessaryportion is selectively etched, so that a stack of the layers 105 b and105 c with a predetermined shape can be obtained.

Alternatively, the layer 105 b and/or the layer 105 c (or part thereof,preferably the layer 105 b) may be a color filter and/or a black matrix.When the layer 105 b and/or the layer 105 c is a color filter and/or ablack matrix, an attachment margin for the substrate provided with thetransistor 100 (the substrate having the insulating surface 200) andanother substrate (e.g., a counter substrate or the like in the displaydevice) can be increased. Alternatively, when a black matrix is providedin the layer 105 b and/or the layer 105 c (or part thereof) near thetransistor 100, light cannot be easily incident on the transistor 100.When light is not easily incident on the transistor 100, the off-statecurrent of the transistor 100 can be reduced and/or degradation of thetransistor 100 can be reduced. For example, as illustrated in FIG. 65B,the black matrix 652 can be provided in part of the layer 105 b. Notethat a plurality of color filters with different colors that overlapwith each other can be used as a black matrix.

Note that a color filter and/or a black matrix is preferably formedusing an organic material; thus, the color filter and/or the blackmatrix is preferably formed in the layer 105 b. Note that thisembodiment is not limited thereto, and a light-blocking conductive filmcan be used as the black matrix.

Alternatively, the thickness of the layer 105 c may be smaller than thethickness of the layer 105 b. When the thickness of the layer 105 c ismade smaller, an electric field caused by the electrode 106 can beadequately applied to the channel. Alternatively, when the thickness ofthe layer 105 b is made larger, unevenness due to the transistor 100 orthe like can be adequately reduced.

Alternatively, for example, in the structure illustrated in FIG. 1A,FIG. 1B, FIG. 2A, FIG. 3A, FIG. 3B, FIG. 9A, or the like, the insulatinglayer 105 in the region 122 may include a stack of the layers 105 a, 105b, and 105 c, and the insulating layer 105 in the region 121 may includea stack of the layers 105 a and 105 c. FIG. 26C, FIG. 26D, FIG. 27B,FIG. 28C, FIG. 28D, and FIG. 34B each illustrate such a structure. Withsuch a structure, when only a necessary portion is etched utilizing adifference in sensitivity to etching (etching selectivity), a stack ofthe layers 105 a, 105 b, and 105 c can be obtained. Accordingly, thethickness of the insulating layer 105 in each region can be easilycontrolled. Alternatively, the regions can adequately have differentfunctions (e.g., a planarization function, an impurity blockingfunction, and a shielding function) depending on film quality.Alternatively, the number of processes can be reduced because part ofthe layer can be formed using a photosensitive material.

Here, the layer 105 a may be an inorganic insulating layer, the layer105 b may be an organic insulating layer, and the layer 105 c may be aninorganic insulating layer. In that case, since an organic material isused, the layer 105 b can be thicker than each of the layers 105 a and105 c. When the layer 105 a is an inorganic insulating layer (preferablya silicon nitride film), for example, an impurity in the layer 105 b canbe prevented from entering the transistor 100. Alternatively, when thelayer 105 c is an inorganic insulating layer (preferably a siliconnitride film), an impurity in the layer 105 b can be prevented fromentering the electrode 106 or the layer over the electrode 106. When thelayer 105 b is an organic insulating layer, the organic insulating layercan be used as a planarization layer, and unevenness due to thetransistor 100 or the like can be reduced. In this manner, a surface onwhich the electrode 110 is formed can be planarized. Thus, for example,in the case where the electrode 110 is used as a pixel electrode, adisplay defect can be reduced. Alternatively, since the thickness of thelayer 105 b can be increased, noise to the pixel electrode can bereduced. Alternatively, the layer 105 a and the layer 105 b can havedifferent film qualities or the layer 105 b and the layer 105 c can havedifferent film qualities. Then, since etching selectivity changesdepending on film quality, only a necessary portion is selectivelyetched, so that a stack of the layers 105 a, 105 b, and 105 c with apredetermined shape can be obtained.

Alternatively, the layer 105 a, the layer 105 b, and/or the layer 105 c(or part thereof, preferably the layer 105 b) may be a color filterand/or a black matrix. When the layer 105 a, the layer 105 b, and/or thelayer 105 c is a color filter and/or a black matrix, an attachmentmargin for the substrate provided with the transistor 100 (the substratehaving the insulating surface 200) and another substrate (e.g., acounter substrate or the like in the display device) can be increased.Alternatively, when a black matrix is provided in the layer 105 a, thelayer 105 b, and/or the layer 105 c (or part thereof) near thetransistor 100, light cannot be easily incident on the transistor 100.When light is not easily incident on the transistor 100, the off-statecurrent of the transistor 100 can be reduced and/or degradation of thetransistor 100 can be reduced. For example, as illustrated in FIG. 65C,the black matrix 652 can be provided in part of the layer 105 b. Notethat a plurality of color filters with different colors that overlapwith each other can be used as a black matrix.

Note that a color filter and/or a black matrix is preferably formedusing an organic material; thus, the color filter and/or the blackmatrix is preferably formed in the layer 105 b. Note that thisembodiment is not limited thereto, and a light-blocking conductive filmcan be used as the black matrix.

Note that each of the layers 105 a, 105 b, and 105 c may be a singlelayer or a stack of a plurality of layers.

This embodiment is obtained by performing change, addition,modification, removal, application, superordinate conceptualization, orsubordinate conceptualization on part or all of Embodiment 1. Thus, thisembodiment can be freely combined or replaced with another embodiment(e.g., Embodiment 1).

Embodiment 3

In this embodiment, one aspect of a semiconductor device or the like(e.g., a display device or a light-emitting device) in the presentinvention is described with reference to drawings.

In the structure described in Embodiment 1 with reference to FIG. 1A,FIG. 1B, FIG. 2A, FIG. 3A, FIG. 3B, FIG. 9A, or the like, the insulatinglayer 105 is made thin in the vicinity of the channel of the transistor100. However, the range of the region (the region 121) where theinsulating layer 105 is made thin is not limited thereto. The range ofthe region 121 may be part of the vicinity of the channel. For example,the structure illustrated in FIG. 1A can be changed into a structureillustrated in FIG. 66A. In FIG. 66A, the range of the region 121 ispart of the vicinity of the channel (the range of the region 121 in FIG.66A is smaller than the range of the region 121 in FIG. 1A). Thestructures illustrated in other than FIG. 1A can be changed similarly.Alternatively, the range of the region 121 may be the vicinity of theentire transistor 100 or larger than the vicinity of the entiretransistor 100. For example, the insulating layer 105 may be made thinin the vicinity of the transistor 100 (e.g., a region where theelectrode 106 overlaps with the electrode 104 a and/or the electrode 104b).

In the structure described in Embodiment 2 with reference to FIG. 1C,FIG. 1D, FIG. 2B, FIG. 3C, FIG. 3D, FIG. 9B, FIG. 26A, FIG. 26B, FIG.27A, FIG. 28A, FIG. 28B, FIG. 34A, FIG. 26C, FIG. 26D, FIG. 27B, FIG.28C, FIG. 28D, FIG. 34B, FIG. 65A, FIG. 65B, FIG. 65C, or the like, thelayer 105 b in the vicinity of the channel of the transistor 100 isremoved and the insulating layer 105 is made thin. However, the regionfrom which the layer 105 b is removed is not limited thereto. The regionfrom which the layer 105 b is removed may be part of the vicinity of thechannel. For example, the structure illustrated in FIG. 1C can bechanged into a structure illustrated in FIG. 66B. In FIG. 66B, the rangeof the region 121 is part of the vicinity of the channel (the range ofthe region 121 in FIG. 66B is smaller than the range of the region 121in FIG. 1C). The structures illustrated in other than FIG. 1C can bechanged similarly. Alternatively, the range of the region 121 may be thevicinity of the entire transistor 100 or larger than the vicinity of theentire transistor 100. For example, in the structure illustrated in FIG.1C, FIG. 1D, FIG. 2B, FIG. 3C, FIG. 3D, FIG. 9B, FIG. 26C, FIG. 26D,FIG. 27B, FIG. 28C, FIG. 28D, or FIG. 34B, the layer 105 b in thevicinity of the channel of the transistor 100 may be removed and theinsulating layer 105 may be made thin. For example, the layer 105 b maybe removed from a region where the electrode 106 overlaps with theelectrode 104 a and/or the electrode 104 b. FIG. 1E, FIG. 2D, FIG. 2C,FIG. 3E, FIG. 2E, FIG. 9C, FIG. 26E, FIG. 27D, FIG. 27C, FIG. 28E, FIG.27E, and FIG. 34C each illustrate this structure.

Note that in the structures illustrated in FIG. 26E, FIG. 27D, FIG. 27C,FIG. 28E, FIG. 27E, and FIG. 34C, one of the layers 105 a and 105 c maybe further removed from part or all of the region from which the layer105 b is removed.

In the structure where the insulating layer 105 is made thin in thevicinity of the transistor 100 (e.g., the region where the electrode 106overlaps with the electrode 104 a and/or the electrode 104 b), thecapacitance value of parasitic capacitance generated by overlapping ofthe electrode 106 with the electrode 104 a and/or the electrode 104 bcan be increased. Thus, the parasitic capacitance can be actively usedas a storage capacitor. For example, the storage capacitor can be usedas a storage capacitor in a pixel. Even when the insulating layer 105 ismade thin in the vicinity of the transistor 100 as described above, inthe case where a fixed potential is applied to the electrode 106, thepotential does not influence the potential of the electrode 104 a and/orthe potential of the electrode 104 b. Note that one aspect of anembodiment of the present invention is not limited thereto.

In contrast, when a variation potential (e.g., a pulse potential) isapplied to the electrode 106 (for example, a signal which is similar toa signal input to the electrode 101 is input to the electrode 106), inorder to reduce the influence of a change in potential applied to theelectrode 106 on the potential of the electrode 104 a and/or thepotential of the electrode 104 b, it is preferable that the insulatinglayer 105 be made thick between the electrode 106 and the electrode 104a and/or the electrode 104 b. For example, it is preferable that thelayer 105 b be provided between the electrode 106 and the electrode 104a and/or the electrode 104 b. In this manner, the influence of a changein potential applied to the electrode 106 on the potential of theelectrode 104 a and/or the potential of the electrode 104 b can bereduced and, for example, noise to a signal input to the electrode 110connected to the electrode 104 b can be prevented. Thus, in the casewhere the electrode 110 is used as a pixel electrode, the displayquality of the display device can be improved. Note that one aspect ofan embodiment of the present invention is not limited thereto.

Note that the electrode 106 may be formed in the entire region 121 or atleast part of the region 121. In the case where the electrode 106 issmall, the degree of overlapping of the electrode 104 a and/or electrode104 b with the electrode 106 is small. Thus, the influence of a changein potential applied to the electrode 106 on the potential of theelectrode 104 a and/or the potential of the electrode 104 b can bereduced.

Alternatively, in the case where a driver circuit (e.g., a scan linedriver circuit or a signal line driver circuit for inputting a signal toa pixel) is formed using the transistors 100, the entire region over thedriver circuit may be the region 121. For example, the entire layer 105b over the driver circuit may be removed. This is because it is notnecessary to provide a display element used for displaying an image overthe driver circuit and it is not necessary to perform planarization withthe use of the layer 105 b. Alternatively, when the entire layer 105 bover the driver circuit is removed, a capacitor (parasitic capacitance)formed by electrodes or wirings can be increased. In this manner, acapacitor (parasitic capacitance) used for bootstrap operation or acapacitor (parasitic capacitance) for a dynamic circuit can beincreased. Alternatively, when the entire layer 105 b over the drivercircuit is removed, a margin for part of the layer 105 b is notnecessary; thus, the layout area of the entire driver circuit can bedecreased. In that case, the electrodes 106 of the plurality oftransistors 100 included in the driver circuit may be electricallyconnected to each other. Alternatively, the electrodes 106 of theplurality of transistors 100 included in the driver circuit may or maynot be isolated from each other.

This embodiment is obtained by performing change, addition,modification, removal, application, superordinate conceptualization, orsubordinate conceptualization on part or all of Embodiment 1 or part orall of Embodiment 2. Thus, this embodiment can be freely combined orreplaced with another embodiment (e.g., Embodiment 1 or 2).

Embodiment 4

In this embodiment, one aspect of a semiconductor device or the like(e.g., a display device or a light-emitting device) in the presentinvention is described with reference to drawings.

Structure examples of a portion where the electrode 110 and theelectrode 104 b are connected to each other in the semiconductor devicesand the like in Embodiments 1 to 3 are described.

Structure examples of a portion where the electrodes 110 and 104 b areconnected to each other in the case of the insulating layer 105including a stack of the layers 105 a and 105 b are described withreference to FIGS. 4A and 4B and FIGS. 5A and 5B.

FIG. 4A illustrates the structure in FIG. 1C and an enlarged view of theportion where the electrodes 110 and 104 b are connected to each otherin the structure. In the enlarged view in FIG. 4A, an end of an openingin the layer 105 a and an end of an opening in the layer 105 b aresubstantially aligned with each other. Such openings can be formed, forexample, in such a manner that a stack of a film A to be the layer 105 aand a film B to be the layer 105 b is formed, and then, the film A andthe film B are etched using one photomask.

The shape of the portion where the electrodes 110 and 104 b areconnected to each other is not limited to the shape illustrated in theenlarged view in FIG. 4A. For example, a shape illustrated in FIG. 4Bmay be used. In FIG. 4B, the end of the opening in the layer 105 a andthe end of the opening in the layer 105 b are not aligned with eachother, and the diameter of the opening in the layer 105 b is larger thanthe diameter of the opening in the layer 105 a (the difference indiameter between the openings is indicated by Δx1 in FIG. 4B). Openingswith such shapes can be formed, for example, in such a manner that thestructure illustrated in the enlarged view in FIG. 4A is formed, andthen, ashing is performed on the layer 105 b. In the case where ashingis performed on the layer 105 b, the layer 105 b is formed using anorganic insulating layer. Note that ashing means that part of a layer isremoved in such a manner that an active oxygen molecule, an ozonemolecule, an oxygen atom, or the like generated by discharge or the likechemically acts on a layer which is an organic substance to ash thelayer. Alternatively, openings with such shapes can be formed in such amanner that a stack of the film A to be the layer 105 a and the film Bto be the layer 105 b is formed, the film A and the film B are etchedusing a photomask, and then, the film B which is etched is furtheretched using a different photomask. Alternatively, openings with suchshapes can be formed in such a manner that a stack of the film A to bethe layer 105 a and the film B to be the layer 105 b is formed, the filmB is etched using a photomask, and then, the film A is etched using adifferent photomask. In the case where the film A and the film B areetched using different photomasks, for example, as illustrated in FIG.5B, the diameter of the opening in the layer 105 b can be much largerthan the diameter of the opening in the layer 105 a as compared to thestructure in FIG. 4B (the difference in diameter between the openings isindicated by Δx3 in FIG. 5B). Alternatively, in the case where the filmA and the film B are etched using different photomasks, for example, asillustrated in FIG. 5A, the diameter of the opening in the layer 105 acan be larger than the diameter of the opening in the layer 105 b (thedifference in diameter between the openings is indicated by Δx2 in FIG.5A).

FIGS. 4A and 4B and FIGS. 5A and 5B each illustrate a structure exampleof the portion where the electrodes 110 and 104 b are connected to eachother in the case of the insulating layer 105 including a stack of thelayers 105 a and 105 b. However, the layered structure of the insulatinglayer 105 is not limited thereto. The shape of the portion where theelectrodes 110 and 104 b are connected to each other can be varieddepending on the layered structure.

For example, FIGS. 29A and 29B each illustrate a structure example ofthe portion where the electrodes 110 and 104 b are connected to eachother in the case of the insulating layer 105 including a stack of thelayers 105 b and 105 c. FIG. 29A illustrates the structure in FIG. 26Aand an enlarged view of the portion where the electrodes 110 and 104 bare connected to each other in the structure. In FIG. 29A, the end ofthe opening in the layer 105 b and an end of an opening in the layer 105c are not aligned with each other, and the diameter of the opening inthe layer 105 b is larger than the diameter of the opening in the layer105 c. In FIG. 29B, the end of the opening in the layer 105 b and theend of the opening in the layer 105 c are not aligned with each other,and the diameter of the opening in the layer 105 c is larger than thediameter of the opening in the layer 105 b.

Openings with the shapes in FIG. 29A or FIG. 29B can be formed, forexample, in such a manner that the film B to be the layer 105 b isformed, the film B is etched using a photomask, a film C to be the layer105 c is formed, and then, the film C is etched using a differentphotomask. Openings with the shapes in FIG. 29B can be formed, forexample, in such a manner that a stack of the film B to be the layer 105b and the film C to be the layer 105 c is formed, the film B and thefilm C are etched using a photomask, and then, the film C which isetched is further etched using a different photomask.

Note that although not illustrated in FIGS. 29A and 29B, the end of theopening in the layer 105 b and the end of the opening in the layer 105 cmay be substantially aligned with each other.

For example, FIGS. 30A and 30B each illustrate a structure example ofthe portion where the electrodes 110 and 104 b are connected to eachother in the case of the insulating layer 105 including a stack of thelayers 105 a, 105 b, and 105 c. FIG. 30A illustrates the structure inFIG. 26C and an enlarged view of the portion where the electrodes 110and 104 b are connected to each other in the structure. In FIG. 30A, theend of the opening in the layer 105 a and the end of the opening in thelayer 105 b are substantially aligned with each other. The end of theopening in the layer 105 a and the end of the opening in the layer 105 bare not aligned with each other, and the diameter of each of theopenings in the layers 105 a and 105 b is larger than the diameter ofthe opening in the layer 105 c. In FIG. 30B, the end of the opening inthe layer 105 a and the end of the opening in the layer 105 c aresubstantially aligned with each other. The end of the opening in thelayer 105 a and the end of the opening in the layer 105 c are notaligned with each other, and the diameter of the opening in the layer105 b is larger than the diameter of each of the openings in the layers105 a and 105 c.

Openings with the shapes in FIG. 30A can be formed, for example, in sucha manner that a stack of the film A to be the layer 105 a and the film Bto be the layer 105 b is formed, the film B and the film A are etchedusing a photomask, the film C to be the layer 105 c is formed, and then,the film C is etched using a different photomask.

Openings with the shapes in FIG. 30B can be formed, for example, in sucha manner that a stack of the film A to be the layer 105 a and the film Bto be the layer 105 b is formed, the film B is etched using a photomask,the film C to be the layer 105 c is formed, and then, the film C and thefilm A are etched using a different photomask.

Note that although not illustrated in FIGS. 30A and 30B, the end of theopening in the layer 105 a, the end of the opening in the layer 105 b,and the end of the opening in the layer 105 c may be aligned with eachother.

Alternatively, a structure may be employed in which the end of theopening in the layer 105 a, the end of the opening in the layer 105 b,and the end of the opening in the layer 105 c are not aligned with eachother. In that case, an end of the layer 105 a may be covered with thelayer 105 b. An end of the layer 105 b may or may not be covered withthe layer 105 c.

Note that in each of the structures illustrated in FIGS. 4A and 4B andFIGS. 5A and 5B, the taper angle of the end of the opening in the layer105 a (indicated by θ2 in FIGS. 4A and 4B and FIGS. 5A and 5B) may besubstantially the same as or different from the taper angle of the endof the opening in the layer 105 b (indicated by θ1 in FIGS. 4A and 4Band FIGS. 5A and 5B). In the structures illustrated in FIGS. 29A and29B, the taper angle of the end of the opening in the layer 105 b(indicated by θ1 in FIGS. 29A and 29B) may be substantially the same asor different from the taper angle of the end of the opening in the layer105 c (indicated by θ3 in FIGS. 29A and 29B). In the structuresillustrated in FIGS. 30A and 30B, all the taper angle of the end of theopening in the layer 105 a (indicated by θ2 in FIGS. 30A and 30B), thetaper angle of the end of the opening in the layer 105 b (indicated byθ1 in FIGS. 30A and 30B), and the taper angle of the end of the openingin the layer 105 c (indicated by θ3 in FIGS. 30A and 30B) may besubstantially the same, two of the taper angles may be substantially thesame, or all the taper angles may be different from each other.

For example, in the case where the thickness of the layer 105 b islarge, θ1 is preferably small in order that the end of the layer 105 bcan be smooth as much as possible. For example, 02 is preferably largerthan 01. Further, θ3 is preferably larger than 01. Note that one aspectof an embodiment of the present invention is not limited thereto.

Here, the taper angle of an end of a layer is an angle formed by a sidesurface of the end of the layer (a tangent at a lower end) and a bottomsurface of the layer when the layer is seen from a cross-sectionaldirection. The taper angle of each layer can be controlled by control ofthe thickness and material of each layer, etching conditions for formingan opening in each layer, and the like.

Note that FIGS. 4A and 4B, FIGS. 5A and 5B, FIGS. 29A and 29B, and FIGS.30A and 30B illustrate structure examples of the portion where theelectrodes 110 and 104 b are connected to each other in the structuresillustrated in FIG. 1C, FIG. 26A, and FIG. 26C. However, a similarstructure can be employed in the portion where the electrodes 110 and104 b are connected to each other in the semiconductor devices inEmbodiments 1 to 3 with the other structures.

Each of the structure examples of the portion where the electrodes 110and 104 b are connected to each other in FIGS. 4A and 4B, FIGS. 5A and5B, FIGS. 29A and 29B, and FIGS. 30A and 30B can be employed as thestructure of a portion where a given electrode provided below theinsulating layer 105 is electrically connected to a given electrodeprovided over the insulating layer 105 through an opening formed in theinsulating layer 105. For example, each of the structure examples of theportion where the electrodes 110 and 104 b are connected to each otherin FIGS. 4A and 4B, FIGS. 5A and 5B, FIGS. 29A and 29B, and FIGS. 30Aand 30B can also be employed as the structure of a portion where anelectrode formed using the same layer as the electrode 110 is connectedto an electrode formed using the same layer as the electrode 104 b. Forexample, each of the structure examples of the portion where theelectrodes 110 and 104 b are connected to each other in FIGS. 4A and 4B,FIGS. 5A and 5B, FIGS. 29A and 29B, and FIGS. 30A and 30B can also beemployed as the structure of a portion where the electrode 110 or anelectrode formed using the same layer as the electrode 110 is connectedto the electrode 101 or an electrode formed using the same layer as theelectrode 101. For example, each of the structure examples of theportion where the electrodes 110 and 104 b are connected to each otherin FIGS. 4A and 4B, FIGS. 5A and 5B, FIGS. 29A and 29B, and FIGS. 30Aand 30B can also be employed as the structure of a portion where theelectrode 106 or an electrode formed using the same layer as theelectrode 106 is connected to the electrode 101 or an electrode formedusing the same layer as the electrode 101. For example, each of thestructure examples of the portion where the electrodes 110 and 104 b areconnected to each other in FIGS. 4A and 4B, FIGS. 5A and 5B, FIGS. 29Aand 29B, and FIGS. 30A and 30B can also be employed as the structure ofa portion where the electrode 106 or an electrode formed using the samelayer as the electrode 106 is connected to the electrode 104 b or anelectrode formed using the same layer as the electrode 104 b.

This embodiment is obtained by performing change, addition,modification, removal, application, superordinate conceptualization, orsubordinate conceptualization on part or all of Embodiment 1, part orall of Embodiment 2, or part or all of Embodiment 3. Thus, thisembodiment can be freely combined or replaced with another embodiment(e.g., any one of Embodiments 1 to 3).

Embodiment 5

In this embodiment, examples of an electrical connection between theelectrode 106 of the transistor 100 and a different electrode or awiring are described. Note that in drawings, the same portions as thosein the drawings in any of the above embodiments are denoted by the samereference numerals, and the description thereof is omitted.

For example, the electrode 106 can be electrically connected to theelectrode 101. With such a connection, the same potential as theelectrode 101 can be supplied to the electrode 106. Thus, the on-statecurrent of the transistor 100 can be increased. FIGS. 6A to 6E, FIGS. 7Ato 7E, FIGS. 8A to 8E, FIGS. 9D and 9E, FIGS. 31A to 31E, FIGS. 32A to32E, FIGS. 33A to 33E, and FIGS. 34D and 34E each illustrate an examplein which the electrode 106 is electrically connected to the electrode101. Note that the electrical connections between the electrodes 106 and101 in these drawings can be similar to those in the variety of drawingsin Embodiments 1 to 4.

Note that in the case where the transistors 100 are provided in pixelsand a pixel matrix constituted of a plurality of pixels is formed, anopening may be formed for each pixel so that the electrode 106 may beelectrically connected to the electrode 101. Accordingly, contactresistance or wiring resistance can be lowered. Alternatively, anopening may be formed for each plurality of pixels so that the electrode106 may be electrically connected to the electrode 101. Accordingly, thelayout area can be reduced. Alternatively, the electrode 106 may beelectrically connected to the electrode 101 in a pixel matrix region oroutside the pixel matrix region. When the electrode 106 is electricallyconnected to the electrode 101 outside the pixel matrix region, thelayout area in the pixel matrix region can be reduced. Accordingly, theaperture ratio can be increased. Note that in the case where a drivercircuit is provided outside the pixel matrix region, it is preferablethat the electrode 106 be electrically connected to the electrode 101 ina region between the driver circuit and the pixel matrix region.

Alternatively, for example, the electrode 106 can be electricallyconnected to the electrode 104 a or the electrode 104 b. With such aconnection, the same potential as the electrode 104 a or the electrode104 b can be supplied to the electrode 106. FIGS. 13A to 13E, FIGS. 14Ato 14E, FIGS. 15A to 15E, FIGS. 38A to 38E, FIGS. 39A to 39E, and FIGS.40A to 40E each illustrate an example in which the electrode 106 isconnected to the electrode 104 b. Note that the electrical connectionsbetween the electrode 106 and the electrode 104 a or the electrode 104 bin these drawings can be similar to those in the variety of drawings inEmbodiments 1 to 4.

Note that in the case where the transistors 100 are provided in pixelsand a pixel matrix constituted of a plurality of pixels is formed, anopening may be formed for each pixel so that the electrode 106 may beelectrically connected to the electrode 104 b. Alternatively, an openingmay be formed for each plurality of pixels so that the electrode 106 maybe electrically connected to the electrode 104 b. Alternatively, theelectrode 106 may be electrically connected to the electrode 104 b in apixel matrix region or outside the pixel matrix region. Thus, as in theabove case, contact resistance or wiring resistance can be reducedand/or the layout area can be reduced.

Alternatively, for example, the electrode 106 can be electricallyconnected to the electrodes 104 b and 110. With such a connection, thesame potential as the electrodes 104 b and 110 can be supplied to theelectrode 106. FIGS. 16A to 16E, FIGS. 17A to 17E, FIGS. 18A to 18E,FIGS. 41A to 41E, FIGS. 42A to 42E, and FIGS. 43A to 43E each illustratean example in which the electrode 106 is connected to the electrodes 104b and 110. Note that in the structures in these drawings, the electrodes110 and 106 are formed using one conductive film, and the electrodes 110and 106 are collectively referred to as the electrode 110. Although theexample in which the electrodes 110 and 106 are formed using oneconductive film is described, this embodiment is not limited thereto.The electrodes 110 and 106 may be formed by etching of differentconductive films. Alternatively, the electrodes 110 and 106 may be incontact with each other to be electrically connected to each other. Notethat the electrical connections between the electrode 106 and theelectrodes 104 b and 110 in these drawings can be similar to those inthe variety of drawings in Embodiments 1 to 4.

Alternatively, for example, the electrode 106 can be electricallyconnected to an electrode 101 a which is formed using the same layer asthe electrode 101. Here, the electrodes 101 and 101 a can be formed byetching of one conductive film with the use of one mask (reticle). Thatis, the electrodes 101 and 101 a are patterned concurrently. Thus, theelectrodes 101 and 101 a have substantially the same material andthickness, for example. FIGS. 10A to 10E, FIGS. 11A to 11E, FIGS. 12A to12E, FIGS. 35A to 35E, FIGS. 36A to 36E, and FIGS. 37A to 37E eachillustrate an example in which the electrode 106 is connected to theelectrode 101 a. Note that the electrical connections between theelectrode 106 and the electrode which is formed using the same layer asthe electrode 101 in these drawings can be similar to those in thevariety of drawings in Embodiments 1 to 4.

Note that in the case where the transistors 100 are provided in pixelsand a pixel matrix constituted of a plurality of pixels is formed, anopening may be formed for each pixel so that the electrode 106 may beelectrically connected to the electrode 101 a. Alternatively, an openingmay be formed for plurality of pixels so that the electrode 106 may beelectrically connected to the electrode 101 a. Alternatively, theelectrode 106 may be electrically connected to the electrode 101 a in apixel matrix region or outside the pixel matrix region. For example, theelectrode 101 a can be a capacitor line provided in the pixel matrix.The capacitor line forms capacitance such as storage capacitance byoverlapping with a different wiring, an electrode, a conductive layer,or the like with an insulating layer provided therebetween.Alternatively, the electrode 101 a can be a gate signal line provided ina different pixel or a different gate signal line in the same pixel.

Alternatively, for example, the electrode 106 can be electricallyconnected to an electrode 104 c which is formed using the same layer asthe electrode 104 a or the electrode 104 b. Here, the electrodes 104 a,104 b, and 104 c can be formed by etching of one conductive film withthe use of one mask (reticle). That is, the electrodes 104 a, 104 b, and104 c are patterned concurrently. Thus, the electrodes 104 a, 104 b, and104 c have substantially the same material and thickness, for example.FIGS. 23A to 23E, FIGS. 24A to 24E, FIGS. 25A to 25E, FIGS. 49A to 49E,FIGS. 50A to 50E, and FIGS. 51A to 51E each illustrate an example inwhich the electrode 106 is connected to the electrode 104 c. Note thatin FIGS. 25A to 25E and FIGS. 51A to 51E, a semiconductor layer 103 awhich is formed using the same layer as the semiconductor layer 103 isprovided below the electrode 104 c. Note that the electrical connectionsbetween the electrode 106 and the electrode which is formed using thesame layer as the electrode 104 a or the electrode 104 b in thesedrawings can be similar to those in the variety of drawings inEmbodiments 1 to 4.

Note that in the case where the transistors 100 are provided in pixelsand a pixel matrix constituted of a plurality of pixels is formed, anopening may be formed for each pixel so that the electrode 106 may beelectrically connected to the electrode 104 c. Alternatively, an openingmay be formed for each plurality of pixels so that the electrode 106 maybe electrically connected to the electrode 104 c. Alternatively, theelectrode 106 may be electrically connected to the electrode 104 c in apixel matrix region or outside the pixel matrix region. For example, theelectrode 104 c can be a capacitor line provided in the pixel matrix.The capacitor line forms capacitance such as storage capacitance byoverlapping with a different wiring, an electrode, a conductive layer,or the like with an insulating layer provided therebetween.Alternatively, the electrode 104 c can be a signal line or a powersupply line provided in a different pixel or a different signal line ora different power supply line in the same pixel.

Here, in the case where the electrode 101 a or the electrode 104 c is acapacitor line, the following structures can be employed.

A structure may be employed in which a capacitor line is provided ineach pixel row (or each pixel column) of the pixel matrix and theelectrode 106 of the transistor 100 in each pixel row (or each pixelcolumn) is electrically connected to the capacitor line provided in thepixel row (or the pixel column). Alternatively, a structure may beemployed in which a capacitor line is provided in each pixel row (oreach pixel column) of the pixel matrix and the electrode 106 of thetransistor 100 in each pixel row (or each pixel column) is electricallyconnected to a capacitor line provided in a pixel row (or a pixelcolumn) adjacent to the pixel row (or the pixel column).

Note that in the case where one pixel of the pixel matrix includes aplurality of subpixels, a structure may be employed in which a capacitorline is provided in each subpixel row (or each subpixel column) and theelectrode 106 of the transistor 100 in each subpixel row (or eachsubpixel column) is electrically connected to the capacitor lineprovided in the subpixel row (or the subpixel column). Alternatively, inthe case where one pixel of the pixel matrix includes a plurality ofsubpixels, a structure may be employed in which a capacitor line isprovided in each pixel row (or each pixel column) and the electrode 106of the transistor 100 in each subpixel row (or each subpixel column) iselectrically connected to the capacitor line provided in the pixel row(or the pixel column). Alternatively, in the case where one pixel of thepixel matrix includes a plurality of subpixels, a structure may beemployed in which a capacitor line is provided in each subpixel row (oreach subpixel column) and the electrode 106 of the transistor 100 ineach subpixel row (or each subpixel column) is electrically connected toa capacitor line provided in a subpixel row (or a subpixel column)adjacent to the subpixel row (or the subpixel column).

A plurality of capacitor lines can be merged into a single capacitorline. For example, a capacitor line can be used in common betweenadjacent pixels (or subpixels). Accordingly, the number of capacitorlines can be reduced.

Note that in the case where the electrode 106 of the transistor 100 iselectrically connected to a capacitor line, a fixed potential(preferably a potential equal to or lower than the lowest potentialapplied to the electrode 101) can be applied to the capacitor line.Thus, the threshold voltage of the transistor 100 can be controlled sothat the transistor 100 can be normally off. Further, noise due tocapacitive coupling with the electrode 101, the electrode 104 a, or thelike can be prevented from being input to the electrode 110.

Note that in the case where the electrode 106 of the transistor 100 iselectrically connected to the capacitor line, a pulse signal can besupplied to the capacitor line. For example, in the case where commoninversion driving is performed, the potential of a counter electrode andthe potential of the capacitor line are changed with the same amplitudevalue in some cases. Even in such a case, when a low potential at whichthe transistor 100 is turned off is supplied to the electrode 106, thethreshold voltage of the transistor 100 can be controlled so that thetransistor 100 can be normally off.

Note that in the case where the electrode 106 of the transistor 100 iselectrically connected to the capacitor line, it is preferable that thesemiconductor layer 103 be not provided between a pair of electrodes(one of which is the capacitor line) of a capacitor. Note that oneaspect of an embodiment of the present invention is not limited thereto.

Note that the electrode 101 a or the electrode 104 c is not limited to acapacitor line, and can be a different wiring. For example, theelectrode 101 a or the electrode 104 may be a power supply line, aninitialization wiring, or the like. For example, the electrode 101 a orthe electrode 104 may be a wiring provided in a pixel circuit in adisplay device including an EL element (e.g., an organic light-emittingelement). Alternatively, the electrode 101 a or the electrode 104 may bea wiring provided in a driver circuit (e.g., a scan line driver circuitor a signal line driver circuit in a display device).

This embodiment is obtained by performing change, addition,modification, removal, application, superordinate conceptualization, orsubordinate conceptualization on part or all of Embodiment 1, part orall of Embodiment 2, part or all of Embodiment 3, or part or all ofEmbodiment 4. Thus, this embodiment can be freely combined or replacedwith another embodiment (e.g., any one of Embodiments 1 to 4).

Embodiment 6

In this embodiment, examples of an electrical connection between theelectrode 101 of the transistor 100 (or an electrode formed using thesame layer as the electrode 101) and the electrode 104 a or theelectrode 104 b of the transistor 100 (or an electrode formed using thesame layer as the electrode 104 a or the electrode 104 b) are describedwith reference to FIGS. 19A to 19D, FIGS. 44A to 44D, and FIGS. 45A to45D. Note that in drawings, the same portions as those in the drawingsin any of the above embodiments are denoted by the same referencenumerals, and the description thereof is omitted.

FIGS. 19A to 19D each illustrate an example of an electrical connectionbetween the electrode 101 a formed using the same layer as the electrode101 of the transistor 100 and the electrode 104 c formed using the samelayer as the electrode 104 a or the electrode 104 b in the case of theinsulating layer 105 including the layers 105 a and 105 b.

In the structure illustrated in FIG. 19A, the electrode 104 c and theelectrode 101 a are electrically connected to each other through anelectrode 110 b in an opening 191 formed in the layers 105 a and 105 band an opening 192 formed in the insulating layer 102 and the layers 105a and 105 b.

In the structure illustrated in FIG. 19B, the electrode 104 c and theelectrode 101 a are electrically connected to each other through theelectrode 110 b in an opening 193 formed in the layer 105 a and anopening 194 formed in the insulating layer 102 and the layer 105 a. Thatis, the layer 105 b is not provided in the portion g 109 where theelectrodes 104 c and 101 a are connected to each other.

Note that the layer 105 b is not necessarily omitted from the entireportion where the electrodes 104 c and 101 a are connected to eachother. For example, as in the structure illustrated in FIG. 19C or FIG.19D, the layer 105 b may be provided in part of the portion 109 wherethe electrodes 104 c and 101 a are connected to each other.

In the structure illustrated in FIG. 19C, the electrodes 104 c and 101 aare electrically connected to each other through the electrode 110 b inan opening 195 formed in the layer 105 a and an opening 196 formed inthe insulating layer 102 and the layers 105 a and 105 b.

In the structure illustrated in FIG. 19D, the electrodes 104 c and 101 aare electrically connected to each other through the electrode 110 b inan opening 197 formed in the layers 105 a and 105 b and an opening 198formed in the insulating layer 102 and the layer 105 a.

Next, FIGS. 44A to 44D each illustrate an example of an electricalconnection between the electrode 101 a formed using the same layer asthe electrode 101 of the transistor 100 and the electrode 104 c formedusing the same layer as the electrode 104 a or the electrode 104 b inthe case of the insulating layer 105 including the layers 105 b and 105c.

In the structure illustrated in FIG. 44A, the electrode 104 c and theelectrode 101 a are electrically connected to each other through theelectrode 110 b in an opening 441 formed in the layers 105 b and 105 cand an opening 442 formed in the insulating layer 102 and the layers 105b and 105 c.

In the structure illustrated in FIG. 44B, the electrode 104 c and theelectrode 101 a are electrically connected to each other through theelectrode 110 b in an opening 443 formed in the layer 105 c and anopening 444 formed in the insulating layer 102 and the layer 105 c. Thatis, the layer 105 b is not provided in the portion 109 where theelectrodes 104 c and 101 a are connected to each other.

Note that the layer 105 b is not necessarily omitted from the entireportion where the electrodes 104 c and 101 a are connected to eachother. For example, as in the structure illustrated in FIG. 44C or FIG.44D, the layer 105 b may be provided in part of the portion 109 wherethe electrodes 104 c and 101 a are connected to each other.

In the structure illustrated in FIG. 44C, the electrodes 104 c and 101 aare electrically connected to each other through the electrode 110 b inan opening 445 formed in the layer 105 c and an opening 446 formed inthe insulating layer 102 and the layers 105 b and 105 c.

In the structure illustrated in FIG. 44D, the electrodes 104 c and 101 aare electrically connected to each other through the electrode 110 b inan opening 447 formed in the layers 105 b and 105 c and an opening 448formed in the insulating layer 102 and the layer 105 c.

Next, FIGS. 45A to 45D each illustrate an example of an electricalconnection between the electrode 101 a formed using the same layer asthe electrode 101 of the transistor 100 and the electrode 104 c formedusing the same layer as the electrode 104 a or the electrode 104 b inthe case of the insulating layer 105 including the layers 105 a, 105 b,and 105 c.

In the structure illustrated in FIG. 45A, the electrodes 104 c and 101 aare electrically connected to each other through the electrode 110 b inan opening 451 formed in the layers 105 a, 105 b, and 105 c and anopening 452 formed in the insulating layer 102 and the layers 105 a, 105b, and 105 c.

In the structure illustrated in FIG. 45B, the electrodes 104 c and 101 aare electrically connected to each other through the electrode 110 b inan opening 453 formed in the layers 105 a and 105 c and an opening 454formed in the insulating layer 102 and the layers 105 a and 105 c. Thatis, the layer 105 b is not provided in the portion 109 where theelectrodes 104 c and 101 a are connected to each other.

Note that the layer 105 b is not necessarily omitted from the entireportion where the electrodes 104 c and 101 a are connected to eachother. For example, as in the structure illustrated in FIG. 45C or FIG.45D, the layer 105 b may be provided in part of the portion 109 wherethe electrodes 104 c and 101 a are connected to each other.

In the structure illustrated in FIG. 45C, the electrodes 104 c and 101 aare electrically connected to each other through the electrode 110 b inan opening 455 formed in the layers 105 a and 105 c and an opening 456formed in the insulating layer 102 and the layers 105 a, 105 b, and 105c.

In the structure illustrated in FIG. 45D, the electrode 104 c and theelectrode 101 a are electrically connected to each other through theelectrode 110 b in an opening 457 formed in the layers 105 a, 105 b, and105 c and an opening 458 formed in the insulating layer 102 and thelayers 105 a and 105 c.

Each of the connections between the electrodes 104 c and 101 a in thisembodiment can be used, for example, as a connection between theelectrode 104 b and the electrode 101 in the case of the diode-connectedtransistor 100. The diode-connected transistor can be used, for example,in a protection circuit, a driver circuit, or the like. Alternatively,the connection between the electrodes 104 c and 101 a can also be usedwhen a gate electrode is connected to a source electrode or a drainelectrode. For example, the connection between the electrodes 104 c and101 a is used when a gate electrode is connected to a source electrodeor a drain electrode in a pixel circuit in which one pixel includes aplurality of transistors or a driver circuit. For example, in a pixelcircuit in which a pixel includes an EL element (e.g., an organiclight-emitting element), a plurality of transistors are provided and agate electrode is connected to a source electrode or a drain electrodein some cases. Alternatively, also in a circuit for driving a gate line,a plurality of transistors are provided.

Further, the openings 191 to 198 in FIGS. 19A to 19D, the openings 441to 448 in FIGS. 44A to 44D, and the openings 451 to 458 in FIGS. 45A to45D can have shapes which are similar to the shapes of the openingsdescribed in Embodiment 4 with reference to FIGS. 4A and 4B, FIGS. 5Aand 5B, FIGS. 29A and 29B, and FIGS. 30A and 30B.

Note that the electrodes 104 c and 101 a can be connected to each otherwithout the use of the electrode 110 b. For example, the electrodes 104c and 101 a can be directly connected to each other in a contact holeformed in the insulating layer 102.

This embodiment is obtained by performing change, addition,modification, removal, application, superordinate conceptualization, orsubordinate conceptualization on part or all of Embodiment 1, part orall of Embodiment 2, part or all of Embodiment 3, part or all ofEmbodiment 4, or part or all of Embodiment 5. Thus, this embodiment canbe freely combined or replaced with another embodiment (e.g., any one ofEmbodiments 1 to 5).

Embodiment 7

In this embodiment, examples of a structure in which the parasiticcapacitance of the transistor 100 is increased or a structure in whichthe capacitance value of a capacitor electrically connected to thetransistor 100 is increased are described with reference to FIGS. 20A to20D, FIGS. 21A to 21D, FIGS. 46A to 46D, and FIGS. 47A to 47D. Note thatin drawings, the same portions as those in the drawings in any of theabove embodiments are denoted by the same reference numerals, and thedescription thereof is omitted.

Note that FIGS. 20A to 20D and FIGS. 21A to 21D each illustrate anexample in which a stack of the layers 105 a and 105 b is used as theinsulating layer 105. FIGS. 46A and 46C and FIGS. 47B and 47C eachillustrate an example in which a stack of the layers 105 b and 105 c isused as the insulating layer 105. FIGS. 46B and 46D and FIGS. 47A and47D each illustrate an example in which a stack of the layers 105 a, 105b, and 105 c is used as the insulating layer 105.

In FIGS. 20A to 20D, FIGS. 21A to 21D, FIGS. 46A to 46D, and FIGS. 47Ato 47D, the entire layer 105 b over the electrode 104 b or most of thelayer 105 b over the electrode 104 b is removed, and the capacitancevalue of parasitic capacitance (or the capacitance value of a capacitorincluding the electrode 104 b and the electrode 106) is large. In FIGS.20A to 20D, FIGS. 21A to 21D, FIGS. 46A to 46D, and FIGS. 47A to 47D,for example, parasitic capacitance is generated and/or a capacitor isformed in a portion 281 surrounded by a dashed line. The capacitancevalue can be adjusted when the shapes of the electrodes 104 b and 106, arange where the layer 105 b over electrode 104 b is removed, and thelike are determined as appropriate.

Note that in FIGS. 20A to 20D, FIGS. 21A to 21D, FIGS. 46A to 46D, andFIGS. 47A to 47D, parasitic capacitance might also be generated betweenthe electrodes 104 b and 101 and/or a capacitor including the electrodes104 b and 101 might be formed. The capacitance value can be adjustedwhen the shapes of the electrodes 104 b and 101 are determined asappropriate.

In this manner, capacitance between a gate and a source of thetransistor 100 can be increased. Alternatively, a capacitor whosecapacitance value is large can be formed. For example, in the case wherethe transistor 100 is used in a circuit for performing bootstrapoperation, the capacitance between the gate and the source is preferablyincreased. Alternatively, when a signal is held in a capacitor in adynamic circuit, the capacitor is preferably large. Thus, the transistor100 with the structure illustrated in FIGS. 20A to 20D, FIGS. 21A to21D, FIGS. 46A to 46D, FIGS. 47A to 47D, or the like is preferably used.

This embodiment is obtained by performing change, addition,modification, removal, application, superordinate conceptualization, orsubordinate conceptualization on part or all of Embodiment 1, part orall of Embodiment 2, part or all of Embodiment 3, part or all ofEmbodiment 4, part or all of Embodiment 5, or part or all of Embodiment6. Thus, this embodiment can be freely combined or replaced with anotherembodiment (e.g., any one of Embodiments 1 to 6).

Embodiment 8

In this embodiment, structure examples of a capacitor included in asemiconductor device or the like (e.g., a display device or alight-emitting device) are described with reference to FIGS. 22A to 22Eand FIGS. 48A to 48E. Note that in drawings, the same portions as thosein the drawings in any of the above embodiments are denoted by the samereference numerals, and the description thereof is omitted.

Note that FIGS. 22A to 22E each illustrate an example in which a stackof the layers 105 a and 105 b is used as the insulating layer 105. FIGS.48A and 48C each illustrate an example in which a stack of the layers105 b and 105 c is used as the insulating layer 105. FIGS. 48B, 48D, and48E each illustrate an example in which a stack of the layers 105 a, 105b, and 105 c is used as the insulating layer 105.

It is possible to form a capacitor that has the electrode 101 a formedusing the same layer as the electrode 101 as one electrode and has theelectrode 104 c formed using the same layer as the electrode 104 a asthe other electrode. FIGS. 22A and 22B each illustrate such an example.In FIGS. 22A and 22B, for example, a capacitor is formed in a portion282 surrounded by a dashed line. Note that an electrode 106 a is formedusing the same layer as the electrode 106. Although FIGS. 22A and 22Beach illustrate an example in which the electrode 106 a is electricallyconnected to the electrode 104 c, one aspect of an embodiment of thepresent invention is not limited thereto. The electrode 106 a is notnecessarily electrically connected to the electrode 104 c. The electrode106 a may be electrically connected to the electrode 101 a or both theelectrodes 101 a and 104 c. Alternatively, the electrode 106 a is notnecessarily provided over the portion 282.

It is possible to form a capacitor that has the electrode 101 a formedusing the same layer as the electrode 101 as one electrode and has theelectrode 106 a as the other electrode. FIGS. 22C to 22E and FIGS. 48Ato 48E each illustrate such an example. In FIGS. 22C to 22E and FIGS.48A to 48E, for example, a capacitor is formed in a portion 283surrounded by a dashed line.

Note that FIG. 22D corresponds to a structure where part of the layer105 b is removed from FIG. 22C. In the structure illustrated in FIG.22D, the layer 105 b in a region 121 c is not provided. Further, FIG.22E corresponds to a structure where the layer 105 b is removed in awider width than the width of the electrode 101 a (in a horizontaldirection in the diagram) in FIG. 22D. Furthermore, FIGS. 48C and 48Deach illustrate a structure in which part of the layer 105 b is removedfrom FIG. 48A or FIG. 48B. In each of the structures illustrated inFIGS. 48C and 48D, the layer 105 b in the region 121 c is not provided.FIG. 48E corresponds to a structure where the layer 105 b is removed ina wider width than the width of the electrode 101 a (in a horizontaldirection in the diagram) in FIG. 48D.

Note that in FIGS. 22A to 22E and FIGS. 48A to 48E, the electrode 106 amay be the electrode 106, the electrode 110, or an electrode formedusing the same layer as the electrode 110. The electrode 101 a may bethe electrode 101. The electrode 104 c may be the electrode 104.

Note that each of the capacitors illustrated in FIGS. 22A to 22E andFIGS. 48A to 48E can be used as the capacitor provided between the gateand the source of the transistor 100. Alternatively, for example, eachof the capacitors illustrated in FIGS. 22A to 22E and FIGS. 48A to 48Ecan be used as a storage capacitor provided in a pixel. Alternatively,each of the capacitors illustrated in FIGS. 22A to 22E and FIGS. 48A to48E can be used as a capacitor for holding a signal in a driver circuit.

This embodiment is obtained by performing change, addition,modification, removal, application, superordinate conceptualization, orsubordinate conceptualization on part or all of Embodiment 1, part orall of Embodiment 2, part or all of Embodiment 3, part or all ofEmbodiment 4, part or all of Embodiment 5, part or all of Embodiment 6,or part or all of Embodiment 7. Thus, this embodiment can be freelycombined or replaced with another embodiment (e.g., any one ofEmbodiments 1 to 7).

Embodiment 9

In this embodiment, examples of materials of the insulating layers, theelectrodes, the semiconductor layers, and the like in Embodiments 1 to 8are described.

The material of the semiconductor layer 103 in the transistor 100 isdescribed below. Note that a similar material can be used for asemiconductor layer formed using the same layer as the semiconductorlayer 103.

The semiconductor layer 103 in the transistor 100 may include a layercontaining an oxide semiconductor (an oxide semiconductor layer). Forexample, a quaternary metal oxide such as an In—Sn—Ga—Zn—O-based oxidesemiconductor; a ternary metal oxide such as an In—Ga—Zn—O-based oxidesemiconductor, an In—Sn—Zn—O-based oxide semiconductor, anIn—Al—Zn—O-based oxide semiconductor, a Sn—Ga—Zn—O-based oxidesemiconductor, an Al—Ga—Zn—O-based oxide semiconductor, aSn—Al—Zn—O-based oxide semiconductor, or a Hf—In—Zn—O-based oxidesemiconductor; a binary metal oxide such as an In—Zn—O-based oxidesemiconductor, a Sn—Zn—O-based oxide semiconductor, an Al—Zn—O-basedoxide semiconductor, a Zn—Mg—O-based oxide semiconductor, aSn—Mg—O-based oxide semiconductor, an In—Mg—O-based oxide semiconductor,or an In—Ga—O-based oxide semiconductor; or a unary metal oxide such asan In—O-based oxide semiconductor, a Sn—O-based oxide semiconductor, ora Zn—O-based oxide semiconductor can be used as the oxide semiconductor.In addition, the oxide semiconductor may contain an element other thanIn, Ga, Sn, and Zn, for example, SiO₂.

For example, an In—Sn—Zn—O-based oxide semiconductor means an oxidesemiconductor containing indium (In), tin (Sn), and zinc (Zn), and thereis no limitation on the composition ratio. For example, anIn—Ga—Zn—O-based oxide semiconductor means an oxide semiconductorcontaining indium (In), gallium (Ga), and zinc (Zn), and there is nolimitation on the composition ratio. An In—Ga—Zn—O-based oxidesemiconductor can be referred to as IGZO.

The oxide semiconductor layer can be formed using an oxide semiconductorfilm. In the case where an In—Sn—Zn—O-based oxide semiconductor film isformed by sputtering, a target which has a composition ratio ofIn:Sn:Zn=1:2:2, 2:1:3, 1:1:1, 20:45:35, or the like in an atomic ratiois used.

In the case where an In—Zn—O-based oxide semiconductor film is formed bysputtering, a target has a composition ratio of In:Zn=50:1 to 1:2 in anatomic ratio (In₂O₃:ZnO=25:1 to 1:4 in a molar ratio), preferablyIn:Zn=20:1 to 1:1 in an atomic ratio (In₂O₃:ZnO=10:1 to 1:2 in a molarratio), more preferably In:Zn=1.5:1 to 15:1 in an atomic ratio(In₂O₃:ZnO=3:4 to 15:2 in a molar ratio). For example, when the targethas an atomic ratio of In:Zn:O=X:Y:Z, Z>1.5X+Y.

In the case where an In—Ga—Zn—O-based oxide semiconductor film is formedby sputtering, a target can have a composition ratio ofIn:Ga:Zn=1:1:0.5, 1:1:1, or 1:1:2 in an atomic ratio.

When the purity of the target is set to 99.99% or higher, alkali metal,a hydrogen atom, a hydrogen molecule, water, a hydroxyl group, hydride,or the like mixed into the oxide semiconductor film can be reduced. Inaddition, with the use of the target, the concentration of alkali metalsuch as lithium, sodium, or potassium can be reduced in the oxidesemiconductor film.

Note that it has been pointed out that an oxide semiconductor isinsensitive to impurities, there is no problem when a considerableamount of metal impurities is contained in the film, and soda-lime glasswhich contains a large amount of alkali metal such as sodium (Na) and isinexpensive can be used (Kamiya, Nomura, and Hosono, “Carrier TransportProperties and Electronic Structures of Amorphous Oxide Semiconductors:The present status”, KOTAI BUTSURI (SOLID STATE PHYSICS), 2009, Vol. 44,pp. 621-633). But such consideration is not appropriate. Alkali metal isnot an element included in an oxide semiconductor and thus is animpurity. Alkaline earth metal is also an impurity in the case wherealkaline earth metal is not included in an oxide semiconductor. Alkalimetal, in particular, Na becomes Na⁺ when an insulating film which is incontact with an oxide semiconductor layer is an oxide and Na diffusesinto the insulating film. In addition, in the oxide semiconductor layer,Na cuts or enters a bond between metal and oxygen which are included inan oxide semiconductor. As a result, for example, degradation ofcharacteristics of a transistor, such as a normally-on state of thetransistor due to a shift in the threshold voltage in a negativedirection, or a decrease in mobility, occurs. A variation incharacteristics also occurs. Such degradation of characteristics of thetransistor and a variation in characteristics due to the impurity areoutstanding when the concentration of hydrogen in the oxidesemiconductor layer is sufficiently low. Thus, when the concentration ofhydrogen in the oxide semiconductor layer is 1×10¹⁸/m³ or lower,preferably 1×10¹⁷/cm³ or lower, the concentration of the impurity ispreferably lowered. Specifically, the measurement value of a Naconcentration by secondary ion mass spectrometry is preferably5×10¹⁶/cm³ or less, more preferably 1×10¹⁶/cm³ or less, still morepreferably 1×10¹⁵/cm³ or less. Similarly, the measurement value of a Liconcentration is preferably 5×10¹⁵/cm³ or less, more preferably1×10¹⁵/cm³ or less. Similarly, the measurement value of a Kconcentration is preferably 5×10¹⁵/cm³ or less, more preferably1×10¹⁵/cm³ or less.

Note that the oxide semiconductor layer may be either amorphous orcrystalline. The oxide semiconductor layer may be either single crystalor non-single-crystal. In the case of non-single-crystal, the oxidesemiconductor layer may be either amorphous or polycrystalline. Further,the oxide semiconductor may have an amorphous structure including acrystalline portion or may be non-amorphous. For the oxide semiconductorlayer, it is possible to use an oxide including a crystal with c-axisalignment (also referred to as c-axis aligned crystal (CAAC)) that has aphase having triangular, hexagonal, regular triangular, or regularhexagonal atomic order when seen from the direction perpendicular to thea-b plane and in which metal atoms are arranged in a layered manner ormetal atoms and oxygen atoms are arranged in a layered manner when seenfrom the direction perpendicular to the c-axis direction.

CAAC is described in detail with reference to FIGS. 69A to 69E, FIGS.70A to 70C, and FIGS. 71A to 71C. Note that in FIGS. 69A to 69E, FIGS.70A to 70C, and FIGS. 71A to 71C, the vertical direction corresponds tothe c-axis direction and a plane perpendicular to the c-axis directioncorresponds to the a-b plane, unless otherwise specified. When terms“upper half” and “lower half” are simply used, they refer to an upperhalf above the a-b plane and a lower half below the a-b plane (an upperhalf and a lower half with respect to the a-b plane). Further, in FIGS.69A to 69E, an O atom surrounded by a circle represents atetracoordinate O atom and an O atom surrounded by a double circlerepresents a tricoordinate O atom.

FIG. 69A illustrates a structure including one hexacoordinate In atomand six tetracoordinate oxygen atoms (hereinafter referred to astetracoordinate O atoms) close to the In atom. A structure in which oneIn atom and oxygen atoms close to the In atom are only illustrated iscalled a subunit here. The structure in FIG. 69A is actually anoctahedral structure, but is illustrated as a planar structure forsimplicity. Note that three tetracoordinate O atoms exist in each of anupper half and a lower half in FIG. 69A. In the subunit illustrated inFIG. 69A, electric charge is 0.

FIG. 69B illustrates a structure including one pentacoordinate Ga atom,three tricoordinate oxygen atoms (hereinafter referred to astricoordinate O atoms) close to the Ga atom, and two tetracoordinate Oatoms close to the Ga atom. All the tricoordinate O atoms exist in thea-b plane. One tetracoordinate O atom exists in each of an upper halfand a lower half in FIG. 69B. An In atom can have the structureillustrated in FIG. 69B because the In atom can have five ligands. In asubunit illustrated in FIG. 69B, electric charge is 0.

FIG. 69C illustrates a structure including one tetracoordinate Zn atomand four tetracoordinate O atoms close to the Zn atom. In FIG. 69C, onetetracoordinate O atom exists in an upper half and three tetracoordinateO atoms exists in a lower half. Alternatively, three tetracoordinate Oatoms may exist in the upper half and one tetracoordinate O atom mayexist in the lower half in FIG. 69C. In a subunit illustrated in FIG.69C, electric charge is 0.

FIG. 69D illustrates a structure including one hexacoordinate Sn atomand six tetracoordinate O atoms close to the Sn atom. In FIG. 69D, threetetracoordinate O atoms exists in each of an upper half and a lowerhalf. In a subunit illustrated in FIG. 69D, electric charge is +1.

FIG. 69E illustrates a subunit including two Zn atoms. In FIG. 69E, onetetracoordinate O atom exists in each of an upper half and a lower half.In the subunit illustrated in FIG. 69E, electric charge is −1.

Here, a group of some of the subunits are referred to as one group, andsome of the groups are referred to as one unit.

Here, a rule of bonding the subunits to each other is described. Thethree 0 atoms in the upper half with respect to the hexacoordinate Inatom in FIG. 69A each have three proximity In atoms in the downwarddirection, and the three O atoms in the lower half each have threeproximity In atoms in the upward direction. The one 0 atom in the upperhalf with respect to the pentacoordinate Ga atom in FIG. 69B has oneproximity Ga atom in the downward direction, and the one O atom in thelower half has one proximity Ga atom in the upward direction. The one Oatom in the upper half with respect to the tetracoordinate Zn atom inFIG. 69C has one proximity Zn atom in the downward direction, and thethree O atoms in the lower half each have three proximity Zn atoms inthe upward direction. In this manner, the number of the tetracoordinateO atoms above the metal atom is equal to the number of the proximitymetal atoms below the tetracoordinate O atoms. Similarly, the number ofthe tetracoordinate O atoms below the metal atom is equal to the numberof the proximity metal atoms above the tetracoordinate O atoms. Sincethe coordination number of the O atom is 4, the sum of the number of theproximity metal atoms below the O atom and the number of the proximitymetal atoms above the O atom is 4. Accordingly, when the sum of thenumber of the tetracoordinate O atoms above the metal atom and thenumber of the tetracoordinate O atoms below another metal atom is 4, thetwo kinds of subunits including the metal atoms can be bonded to eachother. For example, in the case where a hexacoordinate metal (In or Sn)atom is bonded through three tetracoordinate O atoms in the upper half,the hexacoordinate metal atom is bonded to a pentacoordinate metal (Gaor In) atom or a tetracoordinate metal (Zn) atom.

A metal atom having the above coordination number is bonded to anothermetal atom through a tetracoordinate O atom in the c-axis direction.Further, subunits are bonded to each other so that the total electriccharge in a layer structure is 0. Thus, one group is constituted.

FIG. 70A illustrates a model of one group included in a layer structureof an In—Sn—Zn—O-based material. FIG. 70B illustrates a unit includingthree groups. Note that FIG. 70C illustrates atomic order in the case ofthe layer structure in FIG. 70B observed from the x-axis direction.

In FIG. 70A, for simplicity, a tricoordinate O atom is not illustratedand a tetracoordinate O atom is illustrated by a circle; the number inthe circle shows the number of tetracoordinate O atoms. For example,three tetracoordinate O atoms existing in each of an upper half and alower half with respect to a Sn atom are denoted by circled 3.Similarly, in FIG. 70A, one tetracoordinate O atom existing in each ofan upper half and a lower half with respect to an In atom is denoted bycircled 1. FIG. 70A also illustrates a Zn atom close to onetetracoordinate O atom in a lower half and three tetracoordinate O atomsin an upper half, and a Zn atom close to one tetracoordinate O atom inan upper half and three tetracoordinate O atoms in a lower half.

In the group included in the layer structure of the In—Sn—Zn—O-basedmaterial in FIG. 70A, in the order starting from the top, a Sn atomclose to three tetracoordinate O atoms in each of an upper half and alower half is bonded to an In atom close to one tetracoordinate O atomin each of an upper half and a lower half, the In atom is bonded to a Znatom close to three tetracoordinate O atoms in an upper half, the Znatom is bonded to an In atom close to three tetracoordinate O atoms ineach of an upper half and a lower half through one tetracoordinate Oatom in a lower half with respect to the Zn atom, the In atom is bondedto a subunit that includes two Zn atoms and is close to onetetracoordinate O atom in an upper half, and the subunit is bonded to aSn atom close to three tetracoordinate O atoms in each of an upper halfand a lower half through one tetracoordinate O atom in a lower half withrespect to the subunit. Some of the groups are bonded to each other sothat one unit is constituted.

Here, electric charge for one bond of a tricoordinate O atom andelectric charge for one bond of a tetracoordinate O atom can be assumedto be −0.667 and −0.5, respectively. For example, electric charge of ahexacoordinate or pentacoordinate In atom, electric charge of atetracoordinate Zn atom, and electric charge of a pentacoordinate orhexacoordinate Sn atom are +3, +2, and +4, respectively. Thus, electriccharge of a subunit including a Sn atom is +1. Consequently, an electriccharge of −1, which cancels an electric charge of +1, is needed to forma layer structure including a Sn atom. As a structure having an electriccharge of −1, the subunit including two Zn atoms as illustrated in FIG.69E can be given. For example, when one subunit including two Zn atomsis provided for one subunit including a Sn atom, electric charge iscanceled, so that the total electric charge in the layer structure canbe 0.

An In atom can have either five ligands or six ligands. Specifically,when a unit illustrated in FIG. 70B is formed, an In—Sn—Zn—O-basedcrystal (In₂SnZn₃O₈) can be obtained. Note that the layer structure ofthe obtained In—Sn—Zn—O-based crystal can be expressed as a compositionformula, In₂SnZn₂O₇(ZnO)_(m) (m is 0 or a natural number).

The above rule also applies to the following oxides: a quaternary metaloxide such as an In—Sn—Ga—Zn—O-based oxide; a ternary metal oxide suchas an In—Ga—Zn—O-based oxide (also referred to as IGZO), anIn—Al—Zn—O-based oxide, a Sn—Ga—Zn—O-based oxide, an Al—Ga—Zn—O-basedoxide, or a Sn—Al—Zn—O-based oxide; a binary metal oxide such as anIn—Zn—O-based oxide, a Sn—Zn—O-based oxide, an Al—Zn—O-based oxide, aZn—Mg—O-based oxide, a Sn—Mg—O-based oxide, an In—Mg—O-based oxide, oran In—Ga—O-based oxide; or a unary metal oxide such as an In—O-basedoxide, a Sn—O-based oxide, or a Zn—O-based oxide.

For example, FIG. 71A illustrates a model of one group included in alayer structure of an In—Ga—Zn—O-based material.

In the group included in the layer structure of the In—Ga—Zn—O-basedmaterial in FIG. 71A, in the order starting from the top, an In atomclose to three tetracoordinate O atoms in each of an upper half and alower half is bonded to a Zn atom close to one tetracoordinate O atom inan upper half, the Zn atom is bonded to a Ga atom close to onetetracoordinate O atom in each of an upper half and a lower half throughthree tetracoordinate O atoms in a lower half with respect to the Znatom, and the Ga atom is bonded to an In atom close to threetetracoordinate O atoms in each of an upper half and a lower halfthrough one tetracoordinate O atom in a lower half with respect to theGa atom. Some of the groups are bonded to each other so that one unit isconstituted.

FIG. 71B illustrates a unit including three groups. Note that FIG. 71Cillustrates atomic order in the case of the layer structure in FIG. 71Bobserved from the c-axis direction.

Here, since electric charge of a hexacoordinate or pentacoordinate Inatom, electric charge of a tetracoordinate Zn atom, and electric chargeof a pentacoordinate Ga atom are +3, +2, and +3, respectively, electriccharge of a subunit including an In atom, a Zn atom, and a Ga atom is 0.Thus, the total electric charge of a layer structure having acombination of such subunits is always 0.

Here, since electric charge of a hexacoordinate or pentacoordinate Inatom, electric charge of a tetracoordinate Zn atom, and electric chargeof a pentacoordinate Ga atom are +3, +2, and +3, respectively, electriccharge of a subunit including any of an In atom, a Zn atom, and a Gaatom is 0. Thus, the total electric charge of a group having acombination of such subunits is always 0.

An oxide semiconductor film including CAAC (hereinafter also referred toas a CAAC film) can be formed by sputtering. The above material can beused as a target material. In the case where the CAAC film is formed bysputtering, the proportion of an oxygen gas in an atmosphere ispreferably high. In the case where sputtering is performed in a mixedgas of argon and oxygen, for example, the proportion of an oxygen gas ispreferably 30% or higher, more preferably 40% or higher because supplyof oxygen from the atmosphere promotes crystallization of CAAC.

In the case where the CAAC film is formed by sputtering, a substrateover which the CAAC film is formed is heated preferably to 150° C. orhigher, more preferably to 170° C. or higher. This is because the higherthe substrate temperature becomes, the more crystallization of CAAC ispromoted.

After heat treatment is performed on the CAAC film in a nitrogenatmosphere or in vacuum, heat treatment is preferably performed in anoxygen atmosphere or a mixed gas of oxygen and another gas. This isbecause oxygen deficiency due to the former heat treatment can becorrected by supply of oxygen from the atmosphere in the latter heattreatment.

A film surface on which the CAAC film is formed (a deposition surface)is preferably flat. This is because the c-axis approximatelyperpendicular to the deposition surface exists in the CAAC film, so thatdeposition surface irregularities induce generation of grain boundariesin the CAAC film. Thus, planarization treatment such as chemicalmechanical polishing (CMP) is preferably performed on the depositionsurface before the CAAC film is formed. The average roughness of thedeposition surface is preferably 0.5 nm or less, more preferably 0.3 nmor less.

Note that an oxide semiconductor film formed by sputtering or the likecontains moisture or hydrogen (including a hydroxyl group) as animpurity in some cases. In one embodiment of the present invention, inorder to reduce impurities such as moisture or hydrogen in the oxidesemiconductor film (or an oxide semiconductor layer formed using anoxide semiconductor film) (in order to perform dehydration ordehydrogenation), heat treatment is performed on the oxide semiconductorfilm (the oxide semiconductor layer) in a reduced-pressure atmosphere,an inert gas atmosphere of nitrogen, a rare gas, or the like, an oxygengas atmosphere, or ultra dry air (the moisture amount is 20 ppm (−55° C.by conversion into a dew point) or less, preferably 1 ppm or less, morepreferably 10 ppb or less, in the case where measurement is performed bya dew point meter in a cavity ring-down laser spectroscopy (CRDS)method).

By performing heat treatment on the oxide semiconductor film (the oxidesemiconductor layer), moisture or hydrogen in the oxide semiconductorfilm (the oxide semiconductor layer) can be eliminated. Specifically,heat treatment may be performed at a temperature higher than or equal to250° C. and lower than or equal to 750° C., preferably higher than orequal to 400° C. and lower than the strain point of the substrate. Forexample, heat treatment may be performed at 500° C. for 3 to 6 minutes.When RTA is used for the heat treatment, dehydration or dehydrogenationcan be performed in a short time; thus, treatment can be performed evenat a temperature higher than the strain point of a glass substrate.

After moisture or hydrogen in the oxide semiconductor film (the oxidesemiconductor layer) is eliminated in this manner, oxygen is added.Thus, oxygen defects, for example, in the oxide semiconductor film (theoxide semiconductor layer) can be reduced, so that the oxidesemiconductor film (the oxide semiconductor layer) can be intrinsic(i-type) or substantially intrinsic.

Oxygen can be added in such a manner that, for example, an insulatingfilm including a region where the proportion of oxygen is higher thanthe stoichiometric proportion is formed in contact with the oxidesemiconductor film (the oxide semiconductor layer), and then heattreatment is performed. In this manner, excessive oxygen in theinsulating film can be supplied to the oxide semiconductor film (theoxide semiconductor layer). Thus, the oxide semiconductor film (theoxide semiconductor layer) can contain oxygen excessively. Oxygencontained excessively exists, for example, between lattices of a crystalincluded in the oxide semiconductor film (the oxide semiconductorlayer).

Note that the insulating film including a region where the proportion ofoxygen is higher than the stoichiometric proportion may be applied toeither the insulating film placed on an upper side of the oxidesemiconductor film (the oxide semiconductor layer) or the insulatingfilm placed on a lower side of the oxide semiconductor film (the oxidesemiconductor layer) of the insulating films which are in contact withthe oxide semiconductor film (the oxide semiconductor layer); however,it is preferable to apply such an insulating film to both the insulatingfilms which are in contact with the oxide semiconductor film (the oxidesemiconductor layer). The above effect can be enhanced with a structurewhere the oxide semiconductor film (the oxide semiconductor layer) isprovided between the insulating films each including a region where theproportion of oxygen is higher than the stoichiometric proportion, whichare used as the insulating films in contact with the oxide semiconductorfilm (the oxide semiconductor layer) and positioned on the upper sideand the lower side of the oxide semiconductor film (the oxidesemiconductor layer).

Here, the insulating film including a region where the proportion ofoxygen is higher than the stoichiometric proportion may be asingle-layer insulating film or a plurality of insulating films stacked.Note that the insulating film preferably includes impurities such asmoisture or hydrogen as little as possible. When hydrogen is containedin the insulating film, hydrogen enters the oxide semiconductor film(the oxide semiconductor layer) or oxygen in the oxide semiconductorfilm (the oxide semiconductor layer) is extracted by hydrogen, wherebythe oxide semiconductor film has lower resistance (n-type conductivity);thus, a parasitic channel might be formed. Thus, it is important that adeposition method in which hydrogen is not used be employed in order toform the insulating film containing hydrogen as little as possible. Amaterial having a high barrier property is preferably used for theinsulating film. As the insulating film having a high barrier property,a silicon nitride film, a silicon nitride oxide film, an aluminumnitride film, an aluminum oxide film, an aluminum nitride oxide film, orthe like can be used, for example. When a plurality of insulating filmsstacked are used, an insulating film having a low proportion ofnitrogen, such as a silicon oxide film or a silicon oxynitride film, isformed on a side which is closer to the oxide semiconductor film (theoxide semiconductor layer) than the insulating film having a highbarrier property. Then, the insulating film having a high barrierproperty is formed to overlap with the oxide semiconductor film (theoxide semiconductor layer) with the insulating film having a lowproportion of nitrogen sandwiched therebetween. When the insulating filmhaving a high barrier property is used, impurities such as moisture orhydrogen can be prevented from entering the oxide semiconductor film(the oxide semiconductor layer) or the interface between the oxidesemiconductor film (the oxide semiconductor layer) and anotherinsulating film and the vicinity thereof. In addition, the insulatingfilm having a low proportion of nitrogen, such as a silicon oxide filmor a silicon oxynitride film, is formed to be in contact with the oxidesemiconductor film (the oxide semiconductor layer), so that theinsulating film having a high barrier property can be prevented frombeing in direct contact with the oxide semiconductor film (the oxidesemiconductor layer).

Alternatively, addition of oxygen after moisture or hydrogen in theoxide semiconductor film (the oxide semiconductor layer) is eliminatedmay be performed by performing heat treatment on the oxide semiconductorfilm (the oxide semiconductor layer) in an oxygen atmosphere. The heattreatment is performed at, for example, higher than or equal to 100° C.and lower than 350° C., preferably higher than or equal to 150° C. andlower than 250° C. It is preferable that an oxygen gas used for the heattreatment in an oxygen atmosphere do not include water, hydrogen, or thelike. Alternatively, the purity of the oxygen gas which is introducedinto a heat treatment apparatus is preferably 6N (99.9999%) or higher,more preferably 7N (99.99999%) or higher (that is, the impurityconcentration in oxygen is 1 ppm or lower, preferably 0.1 ppm or lower).

Alternatively, addition of oxygen after moisture or hydrogen in theoxide semiconductor film (the oxide semiconductor layer) is eliminatedmay be performed by ion implantation, ion doping, or the like. Forexample, oxygen made to be plasma with a microwave of 2.45 GHz may beadded to the oxide semiconductor film (the oxide semiconductor layer).

The thus formed oxide semiconductor layer can be used as thesemiconductor layer 103 of the transistor 100. In this manner, thetransistor 100 with extremely low off-state current can be obtained.

The semiconductor layer 103 of the transistor 100 may includemicrocrystalline silicon. Microcrystalline silicon is a semiconductorhaving an intermediate structure between amorphous and crystallinestructures (including a single crystal structure and a polycrystallinestructure). In microcrystalline silicon, columnar or needle-likecrystals having a grain size of 2 to 200 nm, preferably 10 to 80 nm,more preferably 20 to 50 nm, still more preferably 25 to 33 nm havegrown in a direction normal to a substrate surface. Thus, grainboundaries are formed at the interface of the columnar or needle-likecrystals in some cases.

The Raman spectrum of microcrystalline silicon, which is a typicalexample, shifts to a lower wavenumber side than 520 cm⁻¹ whichrepresents single crystal silicon. That is, the peak of the Ramanspectrum of microcrystalline silicon is between 520 cm⁻¹ whichrepresents single crystal silicon and 480 cm⁻¹ which representsamorphous silicon. Further, microcrystalline silicon contains hydrogenor halogen at a concentration of at least 1 atomic % to terminate adangling bond. Furthermore, microcrystalline silicon contains a rare gaselement such as helium, argon, krypton, or neon to further promotelattice distortion, so that stability is increased and favorablemicrocrystalline silicon can be obtained. Such microcrystalline siliconis disclosed in, for example, U.S. Pat. No. 4,409,134.

The semiconductor layer 103 of the transistor 100 may include amorphoussilicon. The semiconductor layer 103 of the transistor 100 may includepolycrystalline silicon. Alternatively, the semiconductor layer 103 ofthe transistor 100 may include an organic semiconductor, a carbonnanotube, or the like.

The material of the electrode 110 is described below. Note that asimilar material can be used for an electrode formed using the samelayer as the electrode 110.

The electrode 110 can be formed using a light-transmissive conductivematerial.

As the light-transmissive conductive material, indium tin oxide (ITO),indium tin oxide containing silicon oxide (ITSO), organoindium,organotin, zinc oxide, indium zinc oxide, or the like can be used. Notethat the electrode 110 may have both a light-transmissive region and areflective region. Thus, a transflective display device can be obtained.Alternatively, the electrode 110 may be formed using a reflectiveconductive material. Thus, a reflective display device can be obtained.Alternatively, a top-emission light-emitting device can be obtained inwhich light is emitted to a side opposite to a side in which a pixel isformed.

In particular, in the case where a reflective conductive material isused for the electrode 110, the aperture ratio can be increased when theelectrode 110 is provided above the transistor 100 to overlap with thetransistor 100.

The material of the electrode 106 is described below. Note that asimilar material can be used for an electrode formed using the samelayer as the electrode 106.

The electrode 106 can be formed using a light-transmissive conductivematerial. As the light-transmissive conductive material, indium tinoxide (ITO), indium tin oxide containing silicon oxide (ITSO),organoindium, organotin, zinc oxide, indium zinc oxide, or the like canbe used.

The material of the insulating layer 105 is described below.

The insulating layer 105 may include an organic insulating layer. Theinsulating layer 105 may include an inorganic insulating layer. Theinsulating layer 105 may include a stack of an inorganic insulatinglayer and an organic insulating layer. For example, the layers 105 a and105 c can be inorganic insulating layers. The layer 105 b can be anorganic insulating layer.

In the case where the insulating layer 105 or the layer 105 b is a colorfilter, a green organic insulating layer, a blue organic insulatinglayer, a red organic insulating layer, or the like can be used as theinsulating layer 105 or the layer 105 b. In the case where theinsulating layer 105 or the layer 105 b is a black matrix, a blackorganic insulating layer can be used as the insulating layer 105 or thelayer 105 b.

An acrylic resin, polyimide, polyamide, or the like can be used for theorganic insulating layer. With the use of polyimide, degradation of alight-emitting element formed over the insulating layer 105 or the layer105 b can be reduced. Alternatively, a photosensitive material may beused for the organic insulating layer. A film including a photosensitivematerial can be etched without formation of a resist mask. The organicinsulating layer may be formed by a droplet discharge method such as aninkjet method. Alternatively, a layer which is formed by a dropletdischarge method such as an inkjet method and is etched may be used. Forexample, a layer which is formed by a droplet discharge method such asan inkjet method and is etched using a resist mask may be used.

A silicon oxide film, a silicon nitride film, a silicon oxynitride film,or the like can be used for the inorganic insulating layer.

This embodiment is obtained by performing change, addition,modification, removal, application, superordinate conceptualization, orsubordinate conceptualization on part or all of Embodiment 1, part orall of Embodiment 2, part or all of Embodiment 3, part or all ofEmbodiment 4, part or all of Embodiment 5, part or all of Embodiment 6,part or all of Embodiment 7, or part or all of Embodiment 8. Thus, thisembodiment can be freely combined or replaced with another embodiment(e.g., any one of Embodiments 1 to 8).

Embodiment 10

In this embodiment, one aspect of a method for manufacturing asemiconductor device is described.

FIGS. 59A to 59E illustrate an example of a method for manufacturing asemiconductor device with the structure illustrated in FIG. 1A.

The electrode 101 is formed over the insulating surface 200, theinsulating layer 102 is formed over the electrode 101, and thesemiconductor layer 103 which at least partly overlaps with at leastpart of the electrode 101 with the insulating layer 102 providedtherebetween is formed (FIG. 59A).

The electrodes 104 a and 104 b are formed over the semiconductor layer103. An insulating film 591 is formed over the electrodes 104 a and 104b. The insulating film 591 is formed using a positive photosensitivematerial (FIG. 59B).

Then, the insulating film 591 is subjected to exposure with the use of ahalf-tone mask 592. The half-tone mask 592 has regions 592 a, 592 b, and592 c, and these regions have different transmittances of light used forexposure. Here, (transmittance of the region 592 c)>(transmittance ofthe region 592 b)>(transmittance of the region 592 a) (FIG. 59C).

When the insulating film 591 is subjected to exposure with the use ofthe half-tone mask 592, it is possible to form the insulating layer 105that has the regions 121 and 122 and a through hole 123. The region 121is thinner than the region 122 (FIG. 59D).

After that, the electrode 106 which at least partly overlaps with atleast part of the semiconductor layer 103 with the region 121 providedtherebetween is formed over the insulating layer 105, and at least partof the electrode 110 is formed over at least part of the region 122(FIG. 59E).

In this manner, the semiconductor device can be manufactured.

Note that although the insulating film 591 is formed using a positivephotosensitive material, this embodiment is not limited thereto. Theinsulating film 591 may be formed using a negative photosensitivematerial. Alternatively, the insulating layer 105 may be formed in sucha manner that the insulating film 591 is formed without the use of aphotosensitive material, a resist is formed over the insulating film591, the resist is subjected to exposure with the use of a half-tonemask so that a resist mask is formed, and the insulating film 591 isetched with the use of the resist mask.

FIGS. 60A to 60E illustrate an example of a method for manufacturing asemiconductor device with the structure illustrated in FIG. 1C.

The electrode 101 is formed over the insulating surface 200, and theinsulating layer 102, the semiconductor layer 103, and the electrodes104 a and 104 b are formed. The manufacturing steps up to this stage aresimilar to those in FIGS. 59A and 59B. An insulating film 601 a isformed over the electrodes 104 a and 104 b, and an insulating film 601 bis formed over the insulating film 601 a (FIG. 60A).

Then, a resist 602 is formed over the insulating film 601 b. The resist602 is a positive resist. The resist 602 is subjected to exposure withthe use of a half-tone mask 603. The half-tone mask 603 has regions 603a, 603 b, and 603 c, and these regions have different transmittances oflight used for exposure. Here, (transmittance of the region 603c)>(transmittance of the region 603 b)>(transmittance of the region 603a) (FIG. 60B).

When the resist 602 is subjected to exposure with the use of thehalf-tone mask 603, a resist mask 604 having three regions withdifferent thicknesses is formed (FIG. 60C).

When the insulating films 601 a and 601 b are etched using the resistmask 604, it is possible to form an insulating layer (a stack of thelayers 105 a and 105 b) that has the regions 121 and 122 and the throughhole 123. The region 121 is thinner than the region 122 (FIG. 60D).

After that, the electrode 106 which at least partly overlaps with atleast part of the semiconductor layer 103 with the region 121 providedtherebetween is formed over the layer 105 b, and at least part of theelectrode 110 is formed over at least part of the region 122 (FIG. 60E).

In this manner, the semiconductor device can be manufactured.

Note that although the resist 602 is a positive resist in themanufacturing steps in FIGS. 60A to 60E, this embodiment is not limitedthereto. The resist 602 may be formed using a negative photosensitivematerial. Alternatively, the insulating layer (the stack of the layers105 a and 105 b) may be formed in such a manner that the resist 602 isnot used, the insulating film 601 b is formed using a photosensitivematerial, and the insulating film 601 b is, subjected to exposure withthe use of a half-tone mask.

Although a half-tone mask is used in the manufacturing steps in FIGS.60A to 60E, this embodiment is not limited thereto. For example,manufacturing steps as illustrated in FIGS. 61A to 61D can be employed.

The manufacturing step up to the step in FIG. 61A is similar to that inFIG. 60A.

In the manufacturing steps in FIGS. 61A to 61D, the insulating film 601b is etched so that the region 121 and an opening 124 are formed. Inthis manner, the layer 105 b is formed (FIG. 61B).

After that, the insulating film 601 a which is exposed through theopening 124 is etched so that the through hole 123 is formed. In thatcase, part of the layer 105 b may be further etched. Thus, it ispossible to form an insulating layer (a stack of the layers 105 a and105 b) that has the regions 121 and 122 and the through hole 123. Theregion 121 is thinner than the region 122 (FIG. 61C).

After that, the electrode 106 which at least partly overlaps with atleast part of the semiconductor layer 103 with the region 121 providedtherebetween is formed over the layer 105 b, and at least part of theelectrode 110 is formed over at least part of the region 122 (FIG. 61D).

In this manner, the semiconductor device can be manufactured.

Note that although the insulating films 601 a and 601 b are stacked andthen etched in the manufacturing steps in FIGS. 61A to 61D, thisembodiment is not limited thereto. For example, manufacturing steps asillustrated in FIGS. 62A to 62E can be employed.

The step up to the step of forming the insulating film 601 a (FIG. 62A)is similar to the manufacturing step in FIG. 61A.

After the insulating film 601 a is formed, the insulating film 601 a isetched so that the layer 105 a having an opening 125 is formed (FIG.62B).

Then, the insulating film 601 b is formed to cover the layer 105 a (FIG.62C).

Then, the insulating film 601 b is etched. In that case, part of thelayer 105 a may be further etched. Thus, it is possible to form aninsulating layer (a stack of the layers 105 a and 105 b) that has theregions 121 and 122 and the through hole 123. The region 121 is thinnerthan the region 122 (FIG. 62D).

After that, the electrode 106 which at least partly overlaps with atleast part of the semiconductor layer 103 with the region 121 providedtherebetween is formed over the layer 105 b, and at least part of theelectrode 110 is formed over at least part of the region 122 (FIG. 62E).

In this manner, the semiconductor device can be manufactured.

Note that in the manufacturing steps in FIGS. 60A to 60E, FIGS. 61A to61D, and FIGS. 62A to 62E, the insulating layer 105 is constituted oftwo films (the insulating films 601 a and 601 b), and only one of thefilms is selectively removed so that the regions 121 and 122 are formed.However, this embodiment is not limited thereto. The insulating layer105 may be constituted of m an is a natural number) films, and only n (nis a natural number smaller than m) films among m films may beselectively removed so that the regions 121 and 122 are formed.

For example, FIGS. 63A to 63E illustrate steps of forming the insulatinglayer 105 using three films. The steps in FIGS. 63A to 63E correspond tosteps of manufacturing a semiconductor device with the structureillustrated in FIG. 26C.

The step up to the step in FIG. 63A are similar to the manufacturingstep in FIG. 60A

After the insulating film 601 b is formed, the insulating film 601 b isetched so that the layer 105 b having openings 126 and 127 is formed(FIG. 63B).

Then, an insulating film 601 c is formed to cover the layer 105 b (FIG.63C).

Then, the insulating films 601 a and 601 c are etched so that thethrough hole 123 is formed. Thus, it is possible to form an insulatinglayer (a stack of the layers 105 a, 105 b, and 105 c) that has theregions 121 and 122 and the through hole 123. The region 121 is thinnerthan the region 122 (FIG. 63D).

After that, the electrode 106 which at least partly overlaps with atleast part of the semiconductor layer 103 with the region 121 providedtherebetween is formed over the layer 105 c, and at least part of theelectrode 110 is formed over at least part of the region 122 (FIG. 63E).

In this manner, the semiconductor device can be manufactured.

Note that FIGS. 64A to 64E illustrate steps of forming the insulatinglayer 105 using three films. These steps are different from the steps inFIGS. 63A to 63E. The steps in FIGS. 64A to 64E correspond to steps ofmanufacturing a semiconductor device in the case of the layer 105 bcovering an end of the layer 105 a in the structure illustrated in FIG.26C.

First, an insulating film is etched so that the layer 105 a having anopening 128 a is formed, and then, the insulating film 601 b is formed(FIG. 64A).

The insulating film 601 b is etched so that the layer 105 b having theopening 127 and an opening 128 is formed (FIG. 64B). Here, the opening128 is formed in the opening 128 a and has a smaller diameter than theopening 128 a.

Then, the insulating film 601 c is formed to cover the layer 105 b (FIG.64C).

Then, the insulating film 601 c is etched so that the through hole 123is formed. Thus, it is possible to form an insulating layer (a stack ofthe layers 105 a, 105 b, and 105 c) that has the regions 121 and 122 andthe through hole 123. The region 121 is thinner than the region 122(FIG. 64D).

After that, the electrode 106 which at least partly overlaps with atleast part of the semiconductor layer 103 with the region 121 providedtherebetween is formed over the layer 105 c, and at least part of theelectrode 110 is formed over at least part of the region 122 (FIG. 64E).

In this manner, the semiconductor device can be manufactured.

Note that FIGS. 59A to 59E, FIGS. 60A to 60E, FIGS. 61A to 61D, FIGS.62A to 62E, FIGS. 63A to 63E, and FIGS. 64A to 64E illustrate steps ofmanufacturing semiconductor devices obtained by some modifications ofthe semiconductor device in FIG. 1A, FIG. 1C, or FIG. 26C; however, thesemiconductor devices with the other structures in the above embodimentscan be manufactured similarly.

This embodiment is obtained by performing change, addition,modification, removal, application, superordinate conceptualization, orsubordinate conceptualization on part or all of Embodiment 1, part orall of Embodiment 2, part or all of Embodiment 3, part or all ofEmbodiment 4, part or all of Embodiment 5, part or all of Embodiment 6,part or all of Embodiment 7, part or all of Embodiment 8, or part or allof Embodiment 9. Thus, this embodiment can be freely combined orreplaced with another embodiment (e.g., any one of Embodiments 1 to 9).

Embodiment 11

In this embodiment, an example in which any of the semiconductor devicesin Embodiments 1 to 10 is applied to a display device is described.

Any of the semiconductor devices in Embodiments 1 to 10 can be used fora pixel in a liquid crystal display device or the like.

FIGS. 52A and 52B are examples of a cross-sectional view of a pixel in aliquid crystal display device. FIGS. 52A and 52B are cross-sectionalviews in the case of the semiconductor device with the structureillustrated in FIG. 1C applied to a liquid crystal display device. Notethat in FIGS. 52A and 52B, the same portions as those in FIGS. 1A to 1Eare denoted by the same reference numerals, and the description thereofis omitted.

In FIGS. 52A and 52B, the transistor 100 can be provided in a pixel. Theelectrode 110 can be a pixel electrode. The layer 105 b can be a colorfilter and/or a black matrix.

In FIG. 52A, a protrusion 510 is provided in the region 122. Theprotrusion 510 can function as a spacer. Thus, a gap between a substrateover which the transistor 100 is formed (hereinafter referred to as apixel substrate) and a substrate for sealing a liquid crystal layer(hereinafter referred to as a counter substrate) can be controlled withthe protrusion 510. Note that a black matrix may be formed using theprotrusion 510. Alternatively, the protrusion 510 can function as a ribfor controlling alignment of liquid crystal molecules. With theprotrusion 510, a direction in which liquid crystal molecules arealigned can be controlled.

Note that FIGS. 52A and 52B do not illustrate the liquid crystal layer,an electrode (hereinafter referred to as a counter electrode) whichforms a pair with the pixel electrode, and the counter substrate. Thecounter electrode may be provided using either the pixel substrate orthe counter substrate. Although an alignment film is not illustrated,the alignment film may or may not be provided.

In the structure illustrated in FIG. 52A, as illustrated in FIG. 52B,layers 510 a and 510 b may be provided to fill regions where theinsulating layer 105 is thin or the insulating layer 105 is not provided(for example, regions where the layer 105 b is removed). Thus,unevenness of portions over the pixel substrate that face the liquidcrystal layer can be reduced. The layers 510 a and 510 b may be formedusing a material that is different from or the same as the material ofthe protrusion 510. A black matrix may be formed using any one of or allof the layer 510 a, the layer 510 b, and the protrusion 510. Note thatin FIG. 52B, one of the layers 510 a and 510 b is not necessarilyprovided. For example, only the layer 510 a may be provided.

Note that in FIGS. 52A and 52B, the protrusion 510 and the layers 510 aand 510 b can be obtained by processing of an insulating layer byphotolithography. Alternatively, the protrusion 510 and the layers 510 aand 510 b can be formed using a photosensitive material. Note that theprotrusion 510 and the layers 510 a and 510 b can be formed by a dropletdischarge method such as an inkjet method. Although FIGS. 52A and 52Beach illustrate an example in which the protrusion 510 is provided overthe pixel substrate, this embodiment is not limited thereto. Theprotrusion 510 may be provided on the counter substrate.

Although FIGS. 52A and 52B each illustrate an example in which theprotrusion 510 is provided to overlap with the electrode 110, thisembodiment is not limited thereto. The protrusion 510 can be provided soas not to overlap with the electrode 110. Alternatively, the protrusion510 can be provided so as to overlap with the electrode 110 and so asnot to overlap with another part of the electrode 110. Further, theprotrusion 510 may be provided for each pixel or each plurality ofpixels. The protrusion 510 may be provided to partly overlap with awiring of the pixel or may be provided to partly overlap with the blackmatrix.

Although FIGS. 52A and 52B each illustrate an example in which thesemiconductor device in FIG. 1C is applied to a liquid crystal displaydevice, this embodiment is not limited thereto. Any of the semiconductordevices in Embodiments 1 to 10 can be applied to a liquid crystaldisplay device. For example, any of the semiconductor devices inEmbodiments 1 to 10 can be applied to a liquid crystal display device,and any of the protrusion 510, the layer 510 a, and the layer 510 b canbe provided, as in FIGS. 52A and 52B.

This embodiment is obtained by performing change, addition,modification, removal, application, superordinate conceptualization, orsubordinate conceptualization on part or all of Embodiment 1, part orall of Embodiment 2, part or all of Embodiment 3, part or all ofEmbodiment 4, part or all of Embodiment 5, part or all of Embodiment 6,part or all of Embodiment 7, part or all of Embodiment 8, part or all ofEmbodiment 9, or part or all of Embodiment 10. Thus, this embodiment canbe freely combined or replaced with another embodiment (e.g., any one ofEmbodiments 1 to 10).

Embodiment 12

In this embodiment, an example in which any of the semiconductor devicesin Embodiments 1 to 10 is applied to a display device is described.

Any of the semiconductor devices in Embodiments 1 to 10 can be used fora pixel in a liquid crystal display device or the like, for example.

FIGS. 55A to 55F are examples of a circuit diagram of one pixel in apixel portion of a liquid crystal display device. The pixel includes atransistor, a capacitor, and a liquid crystal element. The pixel furtherincludes a gate signal line 551, a source signal line 552, a capacitorline 553, and the like. The source signal line 552 can also be referredto as a video signal line. Note that one pixel illustrated in each ofFIGS. 55A to 55F includes a subpixel. The transistor 100 in any ofEmbodiments 1 to 10 can be used as the transistor. FIG. 55G shows thesymbols of the transistor used in FIGS. 55A to 55F. FIG. 55G shows thesymbols of the transistor and a correspondence between the symbols ofthe transistor and the transistor 100 in any of Embodiments 1 to 10.

FIG. 55H excerpts the liquid crystal element from FIGS. 55A to 55F. Asillustrated in FIG. 55H, the liquid crystal element includes theelectrode 110 (corresponding to a pixel electrode) and an electrode 550(corresponding to a counter electrode). A liquid crystal layer isprovided between the electrode 110 and the electrode 550.

Further, the parasitic capacitance or the capacitor in Embodiment 7 orEmbodiment 8 can be used as the capacitor in FIGS. 55A to 55F.

Any of the semiconductor devices in Embodiments 1 to 10 can be used fora pixel in a display device including an EL element (e.g., an organiclight-emitting element) (hereinafter referred to as an EL displaydevice) or a light-emitting device.

FIGS. 56A to 56C are examples of a circuit diagram of a pixel in an ELdisplay device. The pixel in FIGS. 56A to 56C includes an EL element560, a transistor 562, a transistor 563, and a capacitor 564. The pixelfurther includes the gate signal line 551, the source signal line 552,the capacitor line 553, a power supply line 561, and the like. Thesource signal line 552 is also referred to as a video signal line. Thetransistor 562 has a function of controlling whether to supply a videosignal to a gate of the transistor 563. The transistor 563 has afunction of controlling current to be supplied to the EL element 560.The transistor 100 in any of Embodiments 1 to 10 can be used as thetransistor. The symbols of the transistor and a correspondence betweenthe symbols of the transistor and the transistor 100 in any ofEmbodiments 1 to 10 are as shown in FIG. 55G.

Further, any of the semiconductor devices in Embodiments 1 to 10 can beused for a driver circuit in a liquid crystal display device, an ELdisplay device, or the like. For example, any of the semiconductordevices in Embodiments 1 to 10 can be used for a driver circuit such asa scan line driver circuit or a signal line driver circuit foroutputting a signal to a pixel. FIGS. 57A and 57B illustrate examples ofpart of the driver circuit. The transistor 100 in any of Embodiments 1to 10 can be used as some or all of transistors (transistors 701, 702,703, 704, 705, 706, 707, 708, 709, 710, 711, 712, 713, 715, 801, 802,803, 804, 805, 806, 807, 808, 809, 810, 811, 812, 813, 814, 815, 816,and 817) included in the driver circuit.

Further, the parasitic capacitance or the capacitor in Embodiment 7 orEmbodiment 8 can be used as a capacitor 714 in FIG. 57A.

This embodiment is obtained by performing change, addition,modification, removal, application, superordinate conceptualization, orsubordinate conceptualization on part or all of Embodiment 1, part orall of Embodiment 2, part or all of Embodiment 3, part or all ofEmbodiment 4, part or all of Embodiment 5, part or all of Embodiment 6,part or all of Embodiment 7, part or all of Embodiment 8, part or all ofEmbodiment 9, part or all of Embodiment 10, or part or all of Embodiment11. Thus, this embodiment can be freely combined or replaced withanother embodiment (e.g., any one of Embodiments 1 to 11).

Embodiment 13

In this embodiment, an example in which any of the semiconductor devicesin Embodiments 1 to 10 is applied to a display device such as a liquidcrystal display device is described.

FIG. 53 and FIGS. 58A and 58B illustrate one aspect of the structure ofa pixel in a liquid crystal display device. A cross-sectional view takenalong line A1-A2 in a top view of FIG. 53 corresponds to FIG. 58A or58B.

In FIG. 53 and FIGS. 58A and 58B, a pixel 530 includes the transistor100, a capacitor 531, and a liquid crystal element (or a displayelement). Note that the pixel 530 may be a subpixel. FIG. 53 and FIGS.58A to 58D illustrate only the electrode 110 corresponding to a pixelelectrode of the liquid crystal element (or the display element), and donot illustrate a counter electrode (a common electrode).

Any of the variety of structures in Embodiments 1 to 10 can be used asthe structure of the transistor 100. Thus, the structure of thetransistor 100 is similar to any of the structures in Embodiments 1 to10. Accordingly, the same portions as those in any of the structures inEmbodiments 1 to 10 are denoted by the same reference numerals, and thedescription thereof is omitted. Note that FIG. 58A illustrates anexample in which the transistor 100 with the structure in FIG. 1A isused. FIG. 58B illustrates an example in which the transistor 100 withthe structure in FIG. 1C is used.

Further, the parasitic capacitance or the capacitor in Embodiment 7 orEmbodiment 8 can be used as the capacitor 531. Note that FIG. 58Aillustrates an example in which the capacitor 531 is formed in theregion 121 c where the insulating layer 105 is made thin. FIG. 58Billustrates an example in which the capacitor 531 is formed in theregion 121 c from which the layer 105 b is removed. The structure of thecapacitor 531 in FIG. 58B corresponds to the structure of the capacitorin FIG. 22D.

The electrode 106 of the transistor 100 is electrically connected to theelectrode 101 a through an opening 501 a. The electrode 101 of thetransistor 100 functions as both a gate electrode of the transistor anda gate line. The electrode 101 a is provided in parallel with theelectrode 101. The electrode 101 a functions as both a wiring forapplying a potential to the electrode 106 of the transistor 100 and acapacitor line in pixels (or subpixels) in an adjacent row. Theelectrode 104 a of the transistor 100 functions as both one of a sourceelectrode and a drain electrode and a source line. The source line isprovided to intersect with the gate line. The electrode 104 b of thetransistor 100 functions as the other of the source electrode and thedrain electrode, and is electrically connected to the electrode 110through an opening 501 b. One of a pair of electrodes of the capacitor531 is the electrode 110, and the other electrode of the capacitor 531is the electrode 101 a.

Note that the electrode 101 a can be foi rued using, for example, thesame layer and the same material as the electrode 101. Note that theelectrodes 101 a and 101 may be formed using different materials.

FIG. 54 and FIGS. 58C and 58D illustrate another aspect of the structureof a pixel in a liquid crystal display device. A cross-sectional viewtaken along line A1-A2 in a top view of FIG. 54 corresponds to FIG. 58Cor 58D.

In FIG. 54 and FIGS. 58C and 58D, the pixel 530 includes the transistor100, a capacitor 532, and a liquid crystal element (or a displayelement). Note that the pixel 530 may be a subpixel.

The structure of the transistor 100 is similar to any of the structuresin Embodiments 1 to 10. Accordingly, the same portions as those in anyof the structures in Embodiments 1 to 10 are denoted by the samereference numerals, and the description thereof is omitted. Note thatFIG. 58C illustrates an example in which the transistor 100 with thestructure in FIG. 1A is used. FIG. 58D illustrates an example in whichthe transistor 100 with the structure in FIG. 1C is used. In thismanner, any of the variety of structures in Embodiments 1 to 10 can beused as the structure of the transistor 100.

Further, the parasitic capacitance or the capacitor in Embodiment 7 orEmbodiment 8 can be used as the capacitor 532. Note that FIG. 58Cillustrates an example in which the capacitor 532 is formed in theregion 121 c where the insulating layer 105 is made thin. FIG. 58Dillustrates an example in which the capacitor 532 is formed in theregion 121 c from which the layer 105 b is removed. The structure of thecapacitor 532 in FIG. 58D corresponds to the structure of the capacitorin FIG. 22E.

The electrode 106 of the transistor 100 is electrically connected to theelectrode 101 a through an opening 502 a. The electrode 101 of thetransistor 100 functions as both a gate electrode of the transistor anda gate line. An electrode 101 b is provided in parallel with theelectrode 101. The electrode 101 b functions as a capacitor line. Theelectrode 104 a of the transistor 100 functions as both one of a sourceelectrode and a drain electrode and a source line. The source line isprovided to intersect with the gate line. The electrode 104 b of thetransistor 100 functions as the other of the source electrode and thedrain electrode, and is electrically connected to the electrode 110through an opening 502 b. One of a pair of electrodes of the capacitor532 is the electrode 110, and the other electrode of the capacitor 532is the electrode 101 b.

Note that the electrode 101 b can be formed using, for example, the samelayer and the same material as the electrode 101. Note that theelectrodes 101 b and 101 may be formed using different materials.

Note that FIG. 54 illustrates an example in which the electrode 110 hasa plurality of openings; however, this embodiment is not limitedthereto. Further, the structure illustrated in FIG. 53 may be astructure in which the electrode 110 has a plurality of openings. Theelectrode 110 can have a given shape.

In FIG. 53, FIG. 54, and FIGS. 58A to 58D, the electrode 110 can be alight-transmissive electrode. Alternatively, the electrode 110 can be anelectrode having both a reflective region and a light-transmissiveregion. When the electrode 110 is an electrode having both a reflectiveregion and a light-transmissive region, the liquid crystal displaydevice can be transflective.

In the case where the electrode 110 is an electrode having both areflective region and a light-transmissive region, the electrode 106 canbe formed using the same layer and the same material as a layer providedwith a reflective electrode included in the reflective region. Thus, thesemiconductor layer 103 of the transistor 100 can be shielded fromlight. The electrode having both the reflective region and thelight-transmissive region can be formed by etching of a stack of alight-transmissive film and a reflective film with the use of ahalf-tone mask.

Note that a display element, a display device which is a deviceincluding a display element, a light-emitting element, and alight-emitting device which is a device including a light-emittingelement can employ various modes and can include various elements. Forexample, a display medium whose contrast, luminance, reflectivity,transmittance, or the like is changed by electromagnetic action, such asan EL (electroluminescence) element (e.g., an EL element includingorganic and inorganic materials, an organic EL element, or an inorganicEL element), an LED (e.g., a white LED, a red LED, a green LED, or ablue LED), a transistor (a transistor which emits light in accordancewith current), an electron emitter, a liquid crystal element, electronicink, an electrophoretic element, an electrowetting element, a gratinglight valve (GLV), a plasma display panel (PDP), a digital micromirrordevice (DMD), a piezoelectric ceramic display, or a carbon nanotube, canbe used as a display element, a display device, a light-emittingelement, or a light-emitting device. Display devices having EL elementsinclude an EL display and the like. Display devices having electronemitters include a field emission display (FED), an SED-type flat paneldisplay (SED: surface-conduction electron-emitter display), and thelike. Display devices having liquid crystal elements include a liquidcrystal display (e.g., a transmissive liquid crystal display, atransflective liquid crystal display, a reflective liquid crystaldisplay, a direct-view liquid crystal display, or a projection liquidcrystal display) and the like. Display devices having electronic ink orelectrophoretic elements include electronic paper and the like.

This embodiment is obtained by performing change, addition,modification, removal, application, superordinate conceptualization, orsubordinate conceptualization on part or all of Embodiment 1, part orall of Embodiment 2, part or all of Embodiment 3, part or all ofEmbodiment 4, part or all of Embodiment 5, part or all of Embodiment 6,part or all of Embodiment 7, part or all of Embodiment 8, part or all ofEmbodiment 9, part or all of Embodiment 10, part or all of Embodiment11, or part or all of Embodiment 12. Thus, this embodiment can be freelycombined or replaced with another embodiment (e.g., any one ofEmbodiments 1 to 12).

Embodiment 14

In this embodiment, an example in which a display device is applied to adisplay module is described.

FIG. 72 illustrates a display module. The display module in FIG. 72includes a housing 901, a display device 902, a backlight unit 903, anda housing 904. The display device 902 is electrically connected to adriver IC 905. Power source voltage or a signal is supplied to thebacklight unit 903 through a terminal 906.

Note that this embodiment is not limited to the display module in FIG.72, and a display module having a touch panel may be used. The displaymodule may have a flexible printed circuit (FPC). In FIG. 72, the driverIC 905 may be electrically connected to the display device 902 through aflexible printed circuit (FPC). Further, the display module may have anoptical film such as a polarizing plate or a retardation film.

This embodiment is obtained by performing change, addition,modification, removal, application, superordinate conceptualization, orsubordinate conceptualization on part or all of Embodiment 1, part orall of Embodiment 2, part or all of Embodiment 3, part or all ofEmbodiment 4, part or all of Embodiment 5, part or all of Embodiment 6,part or all of Embodiment 7, part or all of Embodiment 8, part or all ofEmbodiment 9, part or all of Embodiment 10, part or all of Embodiment11, part or all of Embodiment 12, or part or all of Embodiment 13. Thus,this embodiment can be freely combined or replaced with anotherembodiment (e.g., any one of Embodiments 1 to 13).

Embodiment 15

In this embodiment, examples of electronic devices are described.

FIGS. 67A to 67H and FIGS. 68A to 68D illustrate electronic devices.These electronic devices can include a housing 5000, a display portion5001, a speaker 5003, an LED lamp 5004, operation keys 5005 (including apower switch or an operation switch), a connection terminal 5006, asensor 5007 (a sensor having a function of measuring force,displacement, position, speed, acceleration, angular velocity,rotational frequency, distance, light, liquid, magnetism, temperature,chemical substance, sound, time, hardness, electric field, current,voltage, electric power, radiation, flow rate, humidity, gradient,oscillation, smell, or infrared ray), a microphone 5008, and the like.

FIG. 67A illustrates a portable computer, which can include a switch5009, an infrared port 5010, and the like in addition to the aboveobjects. FIG. 67B illustrates a portable image reproducing deviceprovided with a memory medium (e.g., a DVD reproducing device), whichcan include a second display portion 5002, a memory medium read portion5011, and the like in addition to the above objects. FIG. 67Cillustrates a goggle-type display, which can include the second displayportion 5002, a support 5012, an earphone 5013, and the like in additionto the above objects. FIG. 67D illustrates a portable game machine,which can include the memory medium read portion 5011 and the like inaddition to the above objects. FIG. 67E illustrates a digital camerawith a television reception function, which can include an antenna 5014,a shutter button 5015, an image reception portion 5016, and the like inaddition to the above objects. FIG. 67F illustrates a portable gamemachine, which can include the second display portion 5002, the memorymedium read portion 5011, and the like in addition to the above objects.FIG. 67G illustrates a television receiver, which can include a tuner,an image processing portion, and the like in addition to the aboveobjects. FIG. 67H illustrates a portable television receiver, which caninclude a charger 5017 capable of transmitting and receiving signals andthe like in addition to the above objects. FIG. 68A illustrates adisplay, which can include a support base 5018 and the like in additionto the above objects. FIG. 68B illustrates a camera, which can includean external connection port 5019, a shutter button 5015, an imagereception portion 5016, and the like in addition to the above objects.FIG. 68C illustrates a computer, which can include a pointing device5020, the external connection port 5019, a reader/writer 5021, and thelike in addition to the above objects. FIG. 68D illustrates a mobilephone, which can include a transmitter, a receiver, a tuner of 1 segpartial reception service for mobile phones and mobile terminals, andthe like in addition to the above objects.

The electronic devices illustrated in FIGS. 67A to 67H and FIGS. 68A to68D can have a variety of functions, for example, a function ofdisplaying a lot of information (e.g., a still image, a moving image,and a text image) on a display portion; a touch panel function; afunction of displaying a calendar, date, time, and the like; a functionof controlling processing with a lot of software (programs); a wirelesscommunication function; a function of being connected to a variety ofcomputer networks with a wireless communication function; a function oftransmitting and receiving a lot of data with a wireless communicationfunction; a function of reading a program or data stored in a memorymedium and displaying the program or data on a display portion. Further,the electronic device including a plurality of display portions can havea function of displaying image information mainly on one display portionwhile displaying text information on another display portion, a functionof displaying a three-dimensional image by displaying images whereparallax is considered on a plurality of display portions, or the like.Furthermore, the electronic device including an image receiving portioncan have a function of photographing a still image, a function ofphotographing a moving image, a function of automatically or manuallycorrecting a photographed image, a function of storing a photographedimage in a memory medium (an external memory medium or a memory mediumincorporated in the camera), a function of displaying a photographedimage on the display portion, or the like. Note that functions which canbe provided for the electronic devices illustrated in FIGS. 67A to 67Hand FIGS. 68A to 68D are not limited them, and the electronic devicescan have a variety of functions.

The electronic devices in this embodiment each include a display portionfor displaying some kind of information.

Next, application examples of semiconductor devices are described.

FIG. 68E illustrates an example in which a semiconductor device isincorporated in a building structure. FIG. 68E illustrates a housing5022, a display portion 5023, a remote controller 5024 which is anoperation portion, a speaker 5025, and the like. The semiconductordevice is incorporated in the building structure as a wall-hanging typeand can be provided without requiring a large space.

FIG. 68F illustrates another example in which a semiconductor device isincorporated in a building structure. A display panel 5026 isincorporated in a prefabricated bath unit 5027, so that a bather canview the display panel 5026.

Note that although this embodiment describes the wall and theprefabricated bath unit as examples of the building, structures, thisembodiment is not limited thereto. The semiconductor devices can beprovided in a variety of building structures.

Next, examples in which semiconductor devices are incorporated in movingobjects are described.

FIG. 68G illustrates an example in which a semiconductor device isincorporated in a car. A display panel 5028 is incorporated in a carbody 5029 of the car and can display information related to theoperation of the car or information input from inside or outside of thecar on demand. Note that the display panel 5028 may have a navigationfunction.

FIG. 68H illustrates an example in which a semiconductor device isincorporated in a passenger airplane. FIG. 68H illustrates a usagepattern when a display panel 5031 is provided for a ceiling 5030 above aseat of the passenger airplane. The display panel 5031 is incorporatedin the ceiling 5030 through a hinge portion 5032, and a passenger canview the display panel 5031 by stretching of the hinge portion 5032. Thedisplay panel 5031 has a function of displaying information by theoperation of the passenger.

Note that although bodies of a car and an airplane are illustrated asexamples of moving objects in this embodiment, this embodiment is notlimited to them. The semiconductor devices can be provided for a varietyof objects such as two-wheeled vehicles, four-wheeled vehicles(including cars, buses, and the like), trains (including monorails,railroads, and the like), and vessels.

Note that in this specification and the like, in a diagram or a textdescribed in one embodiment, part of the diagram or the text is takenout, and one embodiment of the invention can be constituted. Thus, inthe case where a diagram or a text related to a certain portion isdescribed, the context taken out from part of the diagram or the text isalso disclosed as one embodiment of the invention, and one embodiment ofthe invention can be constituted. Therefore, for example, in a diagramor a text in which one or more active elements (e.g., transistors ordiodes), wirings, passive elements (e.g., capacitors or resistors),conductive layers, insulating layers, semiconductor layers, organicmaterials, inorganic materials, components, devices, operating methods,manufacturing methods, or the like are described, part of the diagram orthe text is taken out, and one embodiment of the invention can beconstituted. For example, M circuit elements (e.g., transistors orcapacitors) (M is an integer, where M<N) are taken out from a circuitdiagram in which N circuit elements (e.g., transistors or capacitors) (Nis an integer) are provided, and one embodiment of the invention can beconstituted. As another example, M layers (M is an integer, where M<N)are taken out from a cross-sectional view in which N layers (N is aninteger) are provided, and one embodiment of the invention can beconstituted. As another example, M elements (M is an integer, where M<N)are taken out from a flow chart in which N elements (N is an integer)are provided, and one embodiment of the invention can be constituted.

Note that in this specification and the like, in a diagram or a textdescribed in one embodiment, in the case where at least one specificexample is described, it will be readily appreciated by those skilled inthe art that a broader concept of the specific example can be derived.Thus, in the diagram or the text described in one embodiment, in thecase where at least one specific example is described, a broader conceptof the specific example is disclosed as one embodiment of the invention,and one embodiment of the invention can be constituted.

Note that in this specification and the like, a content described in atleast a diagram (or may be part of the diagram) is disclosed as oneembodiment of the invention, and one embodiment of the invention can beconstituted. Thus, when a certain content is described in a diagram, thecontent is disclosed as one embodiment of the invention even when thecontent is not described with a text, and one embodiment of theinvention can be constituted. Similarly, part of a diagram that is takenout from the diagram is disclosed as one embodiment of the invention,and one embodiment of the invention can be constituted.

This application is based on Japanese Patent Application serial no.2011-103344 filed with Japan Patent Office on May 5, 2011, the entirecontents of which are hereby incorporated by reference.

What is claimed is:
 1. (canceled)
 2. A display device comprising: asubstrate; a transistor; an organic resin layer over the transistor; anda conductive layer and a pixel electrode over the organic resin layer,wherein the transistor has an oxide semiconductor layer having a channelformation region, wherein the organic resin layer has a first region anda second region, wherein the first region overlaps with the transistor,wherein a thickness of the second region is larger than a thickness ofthe first region, wherein the conductive layer has a region overlappingwith the first region, and wherein a distance between the substrate andan upper surface of the second region is larger than a distance betweenthe substrate and an upper surface of the first region.
 3. The displaydevice according to claim 2, wherein the transistor has a firstelectrode and a second electrode, wherein one of the first electrode andthe second electrode is a source electrode, and wherein the other of thefirst electrode and the second electrode is a drain electrode.
 4. Thedisplay device according to claim 2, wherein the pixel electrode iselectrically connected to the transistor through an opening in theorganic resin layer.
 5. A display device comprising: a first substrate;a transistor over the first substrate; an organic resin layer over thetransistor; a conductive layer, a pixel electrode and a spacer over theorganic resin layer; and a second substrate, wherein the transistor hasan oxide semiconductor layer having a channel formation region, whereinthe organic resin layer has a first region and a second region, whereinthe first region overlaps with the transistor, wherein a thickness ofthe second region is larger than a thickness of the first region,wherein the spacer is capable to provide a gap between the firstsubstrate and the second substrate, wherein the conductive layer has aregion overlapping with the first region, wherein the pixel electrodeand the spacer have a region overlapping with the second region, andwherein a distance between the first substrate and an upper surface ofthe second region is larger than a distance between the first substrateand an upper surface of the first region.
 6. The display deviceaccording to claim 5, wherein the transistor has a first electrode and asecond electrode, wherein one of the first electrode and the secondelectrode is a source electrode, and wherein the other of the firstelectrode and the second electrode is a drain electrode.
 7. The displaydevice according to claim 5, wherein the pixel electrode is electricallyconnected to the transistor through an opening in the organic resinlayer.
 8. A display device comprising: a first substrate; a transistorover the first substrate; an organic resin layer over the transistor; aconductive layer, a pixel electrode and a spacer over the organic resinlayer; and a second substrate, wherein the transistor has an oxidesemiconductor layer having a channel foil cation region, wherein theorganic resin layer has a first region and a second region, wherein thefirst region overlaps with the transistor, wherein a thickness of thesecond region is larger than a thickness of the first region, whereinthe spacer is capable to provide a gap between the first substrate andthe second substrate, wherein the conductive layer has a regionoverlapping with the first region, wherein the spacer is over the secondregion for each plurality of pixels, wherein the spacer overlaps with awiring of the pixel and the pixel electrode, and wherein a distancebetween the first substrate and an upper surface of the second region islarger than a distance between the first substrate and an upper surfaceof the first region.
 9. The display device according to claim 8, whereinthe transistor has a first electrode and a second electrode, wherein oneof the first electrode and the second electrode is a source electrode,and wherein the other of the first electrode and the second electrode isa drain electrode.
 10. The display device according to claim 8, whereinthe pixel electrode is electrically connected to the transistor throughan opening in the organic resin layer.